Elimination Of Die-Pop Defect By Vacuum Reflow For Ultrathin Die With Warpage In Semiconductor Packaging Assembly

By Amkor - 18 Jan, 2024 - Comments: 0

Semiconductor die thickness is getting thinner over time due to improvement of power efficiency in advance power electronic packages. Ultrathin die with convex warpage can easily deteriorate the solder void removal process during solder reflow, leading to various packaging reliability issues. In particular, a new type of packaging defect phenomenon—die-pop—is observed. Vacuum reflow process... » read more

Challenges Grow For Creating Smaller Bumps For Flip Chips

By Anne Meixner - 18 May, 2023 - Comments: 0

New bump structures are being developed to enable higher interconnect densities in flip-chip packaging, but they are complex, expensive, and increasingly difficult to manufacture. For products with high pin counts, flip-chip [1] packages have long been a popular choice because they utilize the whole die area for interconnect. The technology has been in use since the 1970s, starting with IBM�... » read more

Defect Mitigation And Characterization In Silicon Hardmask Materials

By Brewer Science - 17 Mar, 2021 - Comments: 0

From SPIE Digital Library: In this study, metal contaminants, liquid particle count and on-wafer defects of Si- HMs and filtration removal rates are monitored to determine the effect of filter type, pore size, media morphology, and cleanliness on filtration performance. 5-nm PTFE NTD2 filter having proprietary surface treatment used in this study shows lowest defect count. Authors: Vineet... » read more

Mask Supply Chain Preps For 10nm

By Dylan McGrath - 17 Sep, 2015 - Comments: 0

As the semiconductor industry gears up for the 10nm logic node—now likely to begin in the second half of 2017—the photomask supply chain is preparing to grapple with the associated challenges, including dramatic increases in photomask complexity, write times and data volumes. The 10nm node will require more photomasks per mask set, the ability to print smaller and more complex features, ... » read more

Challenges Mount For EUV Masks

By Mark LaPedus - 17 Oct, 2013 - Comments: 0

ASML Holding’s first production-worthy scanners for extreme ultraviolet (EUV) lithography are expected to ship this year, but there are still a number of challenges to bring the technology into high-volume manufacturing. As before, the three main challenges for EUV are the power sources, resists and photomasks. To date, the resists are making progress, while the EUV power sources remain a ... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Defect

Elimination Of Die-Pop Defect By Vacuum Reflow For Ultrathin Die With Warpage In Semiconductor Packaging Assembly

Challenges Grow For Creating Smaller Bumps For Flip Chips

Defect Mitigation And Characterization In Silicon Hardmask Materials

Mask Supply Chain Preps For 10nm

Challenges Mount For EUV Masks