Fixing DP Errors: Colors Or Rings

By Ann Mutschler - 18 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler With the move to the 20nm manufacturing node, double patterning (DP) became a requirement. In addition, topology changes occurred that demanded very regular structures, marking a significant departure from 28nm design. As a result of this new approach, new errors are popping up, such as DP violation loops, odd cycle violations and anchor path violations. Certain... » read more

Supply Chain Catch-Up

By Ed Sperling - 18 Apr, 2013 - Comments: 0

There always will be a few big companies marching to the latest process node available to them. The problem these days isn’t their commitment to pushing forward. It’s the baggage train following them. It’s getting longer, more diverse, and in some cases, it’s falling out of sync. The foundries are out in front with 14nm finFETs, and they’re already working on 10nm transistors—pos... » read more

Chasing Rabbits

By David Abercrombie - 21 Mar, 2013 - Comments: 0

“Now, here, you see, it takes all the running you can do, to keep in the same place. If you want to get somewhere else, you must run at least twice as fast as that!” —Lewis Carroll, Through the Looking Glass By David Abercrombie As I discussed in my previous article, the use of stitching can greatly reduce the number of double patterning (DP) decomposition violations that a designer ... » read more

Directed Self Assembly, double patterning and crying in beer

By Michael Watts - 20 Mar, 2013 - Comments: 1

In the creative, or desperate, rush to find ways to pattern 10 nm node using double patterning immersion 193nm lithography, a designer from ARM is left “crying in his beer” at the consequent design difficulties. This heart rending admission was one of many insights that came at the sessions on Directed Self Assembly (DSA) at Advanced Lithography. Double Patterning has become the -we have... » read more

Designing with FinFETs: The Opportunities and the Challenges

By Various Writers - 28 Feb, 2013 - Comments: 0

With the help of double-patterning and other advanced lithography techniques, CMOS technology continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs are replacing planar CMOS technology as the device technology of choice at these advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage and dynamic powe... » read more

Good Pattern Flow Ahead For 14, 10nm

By Ann Mutschler - 21 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node. “They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant... » read more

Optical Lithography, Take Two

By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus It’s the worst-kept secret in the industry. Extreme ultraviolet (EUV) lithography has missed the initial stages of the 10nm logic and 1xnm NAND flash nodes. Chipmakers hope to insert EUV by the latter stages of 10nm or by 7nm, but vendors are not counting on EUV in the near term and are preparing their back-up plans. Barring a breakthrough with EUV or other technology, IC ... » read more

A Call To Action: How 20nm Will Change IC Design

By Various Writers - 21 Feb, 2013 - Comments: 0

The 20nm process node represents a turning point for the electronics industry. While it brings tremendous power, performance and area advantages, it also comes with new challenges in such areas as lithography, variability, and complexity. The good news is that these become manageable challenges with 20nm-aware EDA tools when they are used within end-to-end, integrated design flows based on a �... » read more

FinFETs, EUV And Moore’s Law

By Ed Sperling - 21 Feb, 2013 - Comments: 0

GlobalFoundries VP Subramani Kengeri talks about progress and problems with advanced processes with Semiconductor Manufacturing & Design. [youtube vid=_Ang0I1vWdI] » read more

Math Questions

By Ed Sperling - 08 Feb, 2013 - Comments: 0

The race is on. GlobalFoundries, TSMC, Samsung, IBM and Intel are all neck deep in research, test chips, variability, lithography and three-dimensional transistor designs. For the first time, though, the goal very publicly has shifted from performance and area to energy efficiency. Being able to double battery life with existing performance over the next couple nodes could mean smart phones ... » read more

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