Connect To Any Chip With Programmable GPIO

By Geoff Tate - 06 Apr, 2023 - Comments: 0

Your MCU/SoC today may have several options for GPIO connections: UART, SPI, I2C. But there are dozens of variations and kinds of GPIO interface protocols: you don’t have enough pins to provide all of them as hardwired options. As a result, a significant number of your customers either can’t use your chip because they need to connect to another with a GPIO interface you don’t support, ... » read more

The Importance Of Metal Stack Compatibility For Semi IP

By Geoff Tate - 02 Mar, 2023 - Comments: 0

Every foundry and every node is different, but for every foundry/node there are multiple supported metal stacks. Some chips use a lot more metal layers than others. A common rule of thumb is each metal layer increases wafer cost 10%. So, a chip with 5 more metal layers than another will cost 50%+ more. The most complex, high performance chips, including performance FPGAs, typically use AL... » read more

Micro FPGAs And Embedded FPGAs

By Geoff Tate - 02 Feb, 2023 - Comments: 0

When people hear “FPGA” they think “big, expensive, power hungry.” But it doesn’t need to be that way. Renesas has announced their Forge FPGA family. Details are at their website and in one of the many articles that covered their press release. Forge FPGAs show that FPGAs don’t have to be big, power hungry, and expensive. Forge FPGAs are tiny, draw standby current measure... » read more

Manycore-FPGA Architecture Employing Novel Duet Adapters To Integrate eFPGAs in a Scalable, Non-Intrusive, Cache-Coherent Manner (Princeton)

By Technical Paper Link - 16 Jan, 2023 - Comments: 0

A technical paper titled "Duet: Creating Harmony between Processors and Embedded FPGAs" was written by researchers at Princeton University. Abstract "The demise of Moore's Law has led to the rise of hardware acceleration. However, the focus on accelerating stable algorithms in their entirety neglects the abundant fine-grained acceleration opportunities available in broader domains and squan... » read more

Integrating 16nm FPGA Into 28/22nm SoC Without Losing Speed Or Flexibility

By Geoff Tate - 05 Jan, 2023 - Comments: 0

Systems companies like FPGA because it gives parallel processing performance that can outdo processors for many workloads and because it can be reconfigured when standards, algorithms, protocols or customer requirements change. But FPGAs are big, burn a lot of power and are expensive. Customers would like to integrate them into their adjacent SoC if possible. Dozens of customers are now u... » read more

Extending RISC-V Processors In The Field With Codasip Studio & Menta eFPGA

By Codasip - 21 Dec, 2022 - Comments: 0

RISC-V is an open specification that allows an infinite number of implementations. But RISC-V goes beyond that and encourages processor architects to add new instructions to accelerate certain algorithms or application domains, for example DSP, AI/ML, and others, while keeping the base instruction set stable. The new instructions may help with the performance, code size, power consumption, or d... » read more

Solving The Quantum Threat With Post-Quantum Cryptography On eFPGAs

By Flex Logix - 30 Nov, 2022 - Comments: 0

The quantum threat and post-quantum cryptography Advances in quantum computing technology threaten the security of current cryptosystems. Asymmetric cryptography algorithms that are used by modern security protocols for key exchange and digital signatures rely on the complexity of certain mathematical problems. Currently, the main problems used for asymmetric cryptography are integer f... » read more

What’s Really Behind The Adoption Of eFPGA?

By Andy Jaros - 01 Sep, 2022 - Comments: 0

System companies are taking a more proactive role in co-designing their hardware and software roadmaps, so it’s no surprise that they are also driving the adoption of embedded FPGAs (eFPGA). But why and why has it taken so long? Today, most system companies leverage FPGAs to offload intensive compute workloads from the main processor or provide broader IO capability than any packaged ASIC ... » read more

eFPGAs Bring A 10X Advantage In Power And Cost

By Andy Jaros - 07 Jul, 2022 - Comments: 0

eFPGA LUTs will out-ship FPGA LUTs at some point in the near future because of the advantages of reconfigurable logic being built into the chip: cost reduction, lower power, and improved performance. Many systems use FPGAs because they are more efficient than processors for parallel processing and can be programmed with application specific co-processors or accelerators typically found in da... » read more

Chips Can Boost Malware Immunity

By John Koon - 15 Jun, 2022 - Comments: 0

Security is becoming an increasingly important design element, fueled by increasingly sophisticated attacks, the growing use of technology in safety-critical applications, and the rising value of data nearly everywhere. Hackers can unlock automobiles, phones, and smart locks by exploiting system design soft spots. They even can hack some mobile phones through always-on circuits when they are... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

Defining The Chiplet Socket

The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?

by Brian Bailey

tag: eFPGA

Connect To Any Chip With Programmable GPIO

The Importance Of Metal Stack Compatibility For Semi IP

Micro FPGAs And Embedded FPGAs

Manycore-FPGA Architecture Employing Novel Duet Adapters To Integrate eFPGAs in a Scalable, Non-Intrusive, Cache-Coherent Manner (Princeton)

Integrating 16nm FPGA Into 28/22nm SoC Without Losing Speed Or Flexibility

Extending RISC-V Processors In The Field With Codasip Studio & Menta eFPGA

Solving The Quantum Threat With Post-Quantum Cryptography On eFPGAs

What’s Really Behind The Adoption Of eFPGA?

eFPGAs Bring A 10X Advantage In Power And Cost

Chips Can Boost Malware Immunity

Trending Articles

NAND Flash Targets 1,000 Layers

Testing For Thermal Issues Becomes More Difficult

Auto Chip Aging Accelerates In Hot Climates

Is In-Memory Compute Still Alive?

Top-Down Vs. Bottom-Up Chiplet Design

Knowledge Centers
Entities, people and technologies explored