Sidestepping Lithography In Chip Manufacturing

By Katherine Derbyshire - 23 May, 2024 - Comments: 0

Rising lithography costs, shrinking feature sizes, and the need for an alternative to copper are collectively spurring new interest in area-selective deposition. An extension of atomic layer deposition, ASD seeks to build circuit features from the bottom up, without relying on lithography. Lithography will remain a critical tool for the foreseeable future. But it has long been the most expen... » read more

BEOL Integration For The 1.5nm Node And Beyond

By Assawer Soussou - 25 Apr, 2022 - Comments: 0

As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented. These challenges include the need for smaller metal pitches, along with support for new process flows. Process modifications to improve RC performance, reduce edge placement error, and enable challenging manufacturing processes will all be required. To address these challenges, we investigated th... » read more

Strategies For Faster Yield Ramps On 5nm Chips

By Laura Peters - 12 Apr, 2022 - Comments: 0

Leading chipmakers TSMC and Samsung are producing 5nm devices in high volume production and TSMC is forging ahead with plans for first 3nm silicon by year end. But to meet such aggressive targets, engineers must identify defects and ramp yield faster than before. Getting a handle on EUV stochastic defects — non-repeating patterning defects such as microbridges, broken lines, or missing con... » read more

International Roadmap for Devices and Systems lithography roadmap

By Technical Paper Link - 19 Nov, 2021 - Comments: 0

Abstract: "Background: Planned improvements in semiconductor chip performance have historically driven improvements in lithography and this is expected to continue in the future. The International Roadmap for Devices and Systems roadmap helps the industry plan for the future. Aim: The 2021 lithography roadmap shows requirements, possible options, and challenges for the next 15 years. Resul... » read more

Multi-Patterning EUV Vs. High-NA EUV

By Mark LaPedus - 04 Dec, 2019 - Comments: 4

Foundries are finally in production with EUV lithography at 7nm, but chip customers must now decide whether to implement their next designs using EUV-based multiple patterning at 5nm/3nm or wait for a new single-patterning EUV system at 3nm and beyond. This scenario revolves around ASML’s current extreme ultraviolet (EUV) lithography tool (NXE:3400C) versus a completely new EUV system with... » read more

Using Sensor Data To Improve Yield And Uptime

By Ed Sperling - 21 Feb, 2019 - Comments: 2

Semiconductor equipment vendors are starting to add more sensors into their tools in an effort to improve fab uptime and wafer yield, and to reduce cost of ownership and chip failures. Massive amounts of data gleaned from those tools is expected to provide far more detail than in the past about multiple types and sources of variation, including when and where that variation occurred and how,... » read more

Variation Issues Grow Wider And Deeper

By Ed Sperling - 24 Jan, 2019 - Comments: 0

Variation is becoming more problematic as chips become increasingly heterogeneous and as they are used in new applications and different locations, sparking concerns about how to solve these issues and what the full impact will be. In the past, variation in semiconductors was considered a foundry issue, typically at the most advanced process node, and largely ignored by most companies. New p... » read more

Where Is Selective Deposition?

By Mark LaPedus - 25 Jun, 2018 - Comments: 4

For years, the industry has been working on an advanced technology called area-selective deposition for chip production at 5nm and beyond. Area-selective deposition, an advanced self-aligned patterning technique, is still in R&D amid a slew of challenges with the technology. But the more advanced forms of technology are beginning to make some progress, possibly inching closer from the la... » read more

New Patterning Options Emerging

By Mark LaPedus - 19 Apr, 2018 - Comments: 1

Several fab tool vendors are rolling out the next wave of self-aligned patterning technologies amid the shift toward new devices at 10/7nm and beyond. Applied Materials, Lam Research and TEL are developing self-aligned technologies based on a variety of new approaches. The latest approach involves self-aligned patterning techniques with multi-color material schemes, which are designed for us... » read more

More Lithography/Mask Challenges (Part 2)

By Mark LaPedus - 17 Apr, 2018 - Comments: 3

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; Regina Freed, managing director of patterning technology at [getentity id="... » read more

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Entities, people and technologies explored

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Partitioning In The Chiplet Era

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3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

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AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?