Cut Power + Cost 5 – 10x: Integrate FPGA In Your SoC

By Flex Logix - 06 Dec, 2023 - Comments: 0

FPGA chips are high cost devices with a high profit margin for the manufacturer: this goes away when you integrate. FPGA packages are large and expensive because of the large number of very high speed signals that require expensive signal integrity design and packaging layers. When you integrate this goes away. And you save the board area the FPGA package took; and eliminate expensive voltage r... » read more

eFPGA Architectural Improvements That Lower Test Cost And Increase Quality

By Geoff Tate - 02 Nov, 2023 - Comments: 0

More than 40 chips have been licensed to use EFLX eFPGA and >20 chips are working in silicon. Big customers like Renesas are planning high volume families of chips using embedded FPGA. As a result, we have gained extensive experience and knowledge in almost 10 years of doing eFPGA especially in production test for cost reduction and reliability improvement. eFPGA DFT and MBIST for high q... » read more

The Challenge And Value Proposition of eFPGA Emulation

By Cheng Wang - 05 Oct, 2023 - Comments: 0

More than 40 chips have been licensed to use EFLX eFPGA and more than 20 chips are already working in silicon. Big customers like Renesas are planning high volumes and families of chips using eFPGA. eFPGA is being used in process nodes from 180nm to 5nm, with 3nm and 18A in evaluation. Especially for the high-volume customers working in advanced finFET nodes, the strong need is for first ... » read more

Taking eFPGA Security To The Next Level

By Flex Logix - 04 Oct, 2023 - Comments: 0

Security is an important topic for every SOC, but it’s especially salient in the context of high-risk assets included in the eFPGA for obfuscation. Whether the device is used in defense systems or in cars driving around town, encryption is important so the device remains secure and can’t be modified maliciously, whether through physical attacks or remote hacking. There are several different... » read more

Use Cases And Value Proposition Of eFPGA

By Geoff Tate - 07 Sep, 2023 - Comments: 0

Flex Logix EFLX eFPGA is the first eFPGA that enables a customer to match the performance of FPGAs from AMD/Xilinx and Intel (in the same process node) with the same density (LUTs/mm2). EFLX eFPGA has been in use with customers now for more than 5 years, hardware and software. More than 40 chips have been licensed to use EFLX eFPGA and more than 20 chips are working in silicon. Big customers... » read more

The Next Generation Of Embedded FPGA

By Geoff Tate - 03 Aug, 2023 - Comments: 0

EFLX eFPGA has been in use in SoCs for more than 5 years, hardware and software. More than 40 chips have been licensed to use EFLX eFPGA and more than 20 chips are working in silicon. Big customers like Renesas are planning high volumes and families of chips using eFPGA. As we have worked with customers our architecture has evolved from EFLX Gen 1.0 to Gen 2.0, 2.1, 2.2, 2.3 and now in 2023 ... » read more

Fully Reconfigurable DSP: As Fast As Hardwired At ~2x Area/Power

By Jeremy Roberson - 01 Jun, 2023 - Comments: 0

Today if you want high performance DSP you have three choices: Hardwire your function – zero flexibility Use DSP IP based on VLIW Use FPGAs with DSP MACs or math engines What we hear from customers is that there is a growing need for very fast and very flexible DSP, which hardwired solutions can’t address. And that the fastest solutions are FPGAs, but they are big, high pow... » read more

Modular FPGA Makes FPGA Easier To Use

By Flex Logix - 31 May, 2023 - Comments: 0

Traditionally FPGAs are configured once at boot/power-on. This is because they almost always store the configuration file in a Flash memory which is updated from time to time (like your smart phone’s OS and apps). But eFPGA is in your SoC, so you can provide the configuration files from on chip SRAM, on chip NVM and/or off chip DRAM. EFLX eFPGA is reconfigurable. Process nodes like 40nm... » read more

Improving Image Resolution At The Edge

By Ed Sperling - 30 May, 2023 - Comments: 0

How much cameras see depends on how accurately the images are rendered and classified. The higher the resolution, the greater the accuracy. But higher resolution also requires significantly more computation, and it requires flexibility in the design to be able to adapt to new algorithms and network models. Jeremy Roberson, technical director and software architect for AI/ML at Flex Logix, talks... » read more

Issues And Challenges In Super-Resolution Object Detection And Recognition

By Jeremy Roberson - 04 May, 2023 - Comments: 0

If you want high performance AI inference, such as Super-Resolution Object Detection and Recognition, in your SoC the challenge is to find a solution that can meet your needs and constraints. You need inference IP that can run the model you want at high accuracy. You need inference IP that can run the model at the frame rate you want: higher frame rate = lower latency, more time for dec... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

Defining The Chiplet Socket

The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?

by Brian Bailey

tag: eFPGA

Cut Power + Cost 5 – 10x: Integrate FPGA In Your SoC

eFPGA Architectural Improvements That Lower Test Cost And Increase Quality

The Challenge And Value Proposition of eFPGA Emulation

Taking eFPGA Security To The Next Level

Use Cases And Value Proposition Of eFPGA

The Next Generation Of Embedded FPGA

Fully Reconfigurable DSP: As Fast As Hardwired At ~2x Area/Power

Modular FPGA Makes FPGA Easier To Use

Improving Image Resolution At The Edge

Issues And Challenges In Super-Resolution Object Detection And Recognition

Trending Articles

NAND Flash Targets 1,000 Layers

Testing For Thermal Issues Becomes More Difficult

Auto Chip Aging Accelerates In Hot Climates

Is In-Memory Compute Still Alive?

Top-Down Vs. Bottom-Up Chiplet Design

Knowledge Centers
Entities, people and technologies explored