The Race To Design Larger Systems

By Ed Sperling - 25 Oct, 2018 - Comments: 0

For more than a decade, tools vendors and design houses have been talking about leveraging their tools and expertise to help design systems of systems. They're finally getting their chance. The basic idea behind this strategy has always been that issues inside any electronic system—performance, power, signal integrity, area—have all been dealt all the way down to the sub-atomic level in ... » read more

What Makes A Good AI Accelerator

By Ann Mutschler - 25 Oct, 2018 - Comments: 3

The rapid growth and dynamic nature of AI and machine learning algorithms is sparking a rush to develop accelerators that can be optimized for different types of data. Where one general-purpose processor was considered sufficient in the past, there are now dozens vying for a slice of the market. As with any optimized system, architecting an accelerator — which is now the main processing en... » read more

A Crisis In DoD’s Trusted Foundry Program?

By Mark LaPedus - 22 Oct, 2018 - Comments: 0

The U.S. Department of Defense’s Trusted Foundry program is in flux due to GlobalFoundries’ recent decision to put 7nm on hold, raising national security concerns across the U.S. defense community. U.S. DoD and military/aerospace chip customers currently have access to U.S.-based “secure” foundry capacity down to 14nm, but that's where it ends. No other foundries provide similar “s... » read more

Reconfigurable eFPGA For Aerospace Applications

By Geoff Tate - 12 Oct, 2018 - Comments: 0

Market research reports indicate about 10% of all dollar revenue of FPGA chips is for use in aerospace applications, and DARPA/DoD reports indicate about one-third of all dollar volume of ICs purchased by U.S. aerospace are FPGAs. FPGAs clearly are very important for aerospace applications because of a combination of short development time and the long mission life of many aerospace applica... » read more

Using ASICs For AI Inferencing

By Ed Sperling - 10 Oct, 2018 - Comments: 0

Flex Logix’s Cheng Wang looks at why ASICs are the best way to improve performance and optimize power and area for inferencing, and how to add flexibility into those designs to deal with constantly changing algorithms and data sets. https://youtu.be/XMHr7sz9JWQ » read more

eFPGA vs. FPGA Design Methodologies

By Ed Sperling - 05 Oct, 2018 - Comments: 0

Namit Varma, senior director of Achronix’s India Technology Center, discusses the differences between discrete and embedded FPGAs. https://youtu.be/Vwo3ktQvcKc » read more

Achieving eFPGA Timing Closure In An ASIC

By Alok Sanghavi - 04 Oct, 2018 - Comments: 0

When we start school as young children, one of the first lessons we learn is how to share, followed quickly by not running with scissors. As Kent Orthner, Achronix’s senior director of Systems Engineering, discussed at the Design Automation Conference in June, sharing is also key when it comes to closing timing with embedded FPGAs (eFPGAs). With an eFPGA, such as Achronix’s Speedcore IP,... » read more

Performance Benchmarking Embedded FPGAs

By Flex Logix - 03 Oct, 2018 - Comments: 0

When evaluating the performance of an embedded FPGA, one needs to evaluate the performance of each of the individual modules that make up an FPGA. The basic modules are: Reconfigurable logic building blocks (RBB-Logic), Fine-granularity logic containing LUTs, carry-forwarding adder chain, and flip-flops Reconfigurable DSP building blocks (RBB-DSP), Medium-granularity arith... » read more

Deriving Configuration Time For eFPGAs

By Volkan Oktem - 06 Sep, 2018 - Comments: 0

Part 1 of this blog post described how to configure an eFPGA, using Achronix’s Speedcore eFPGA as an example. It explained why each instance of the eFPGA in an ASIC or SoC design must be configured after the system powers up due to its nonvolatile SRAM technology to store configuration bits. This post will detail how the configuration time is derived, once again using Speedcore eFPGA as th... » read more

Flexible, Energy-Efficient Neural Network Processing At 16nm

By Geoff Tate - 06 Sep, 2018 - Comments: 0

At Hot Chips 30, held in August in Silicon Valley, Harvard University (Paul Whatmough, SK Lee, S Xi, U Gupta, L Pentecost, M Donato, HC Hseuh, Professor Brooks and Professor Gu) made a presentation on “SMIV: A 16nm SoC with Efficient and Flexible DNN Acceleration for Intelligent IOT Devices. ” (Their complete presentation is available now on the Hot Chips website for attendees and will be p... » read more

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tag: eFPGA

The Race To Design Larger Systems

What Makes A Good AI Accelerator

A Crisis In DoD’s Trusted Foundry Program?

Reconfigurable eFPGA For Aerospace Applications

Using ASICs For AI Inferencing

eFPGA vs. FPGA Design Methodologies

Achieving eFPGA Timing Closure In An ASIC

Performance Benchmarking Embedded FPGAs

Deriving Configuration Time For eFPGAs

Flexible, Energy-Efficient Neural Network Processing At 16nm

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