tag: electromigration

System-Aware SoC Power, Noise And Reliability Signoff
By Ansys - 09 Jul, 2014 - Comments: 0

In globally competitive markets for mobile, consumer and automotive electronic systems, the critical success factors are power consumption, performance and reliability. To manage these conflicting requirements, design teams consider multiple options, including the use of advanced process technology nodes — especially FinFET-based devices. These advanced technology nodes allow chips to operate... » read more

How Much Will That Chip Cost?
By Ed Sperling - 27 Mar, 2014 - Comments: 1

From the most advanced process nodes to the trailing edge of design there is talk about the skyrocketing cost of developing increasingly complex SoCs. At 16/14nm it’s a combination of multi-patterning, multiple power domains and factoring in physical and proximity effects. At older nodes, it’s the shift to more sophisticated versions of the processes and new tools to work within those proce... » read more

More Pain In More Places
By Ed Sperling - 14 Mar, 2014 - Comments: 2

Pain is nothing new in to the semiconductor industry. In fact, the pain of getting complex designs completed on budget, and finding the bugs in those designs, has been responsible for decades of continuous growth in EDA, IP, test, packaging, and foundries. But going forward there is change afoot in every segment of the flow from architecture to design to layout to verification to manufacturi... » read more

FinFET Reliability Issues
By Arvind Vel - 13 Mar, 2014 - Comments: 0

The 16nm FinFET node has introduced several new challenges in the IC design community. In addition to the complexity of power-noise and electromigration (EM) verification, thermal reliability has become a major concern for both chip and package designers. With the three-dimensional architecture of FinFET devices, new simulation approaches are being used to model thermal behavior of the die in o... » read more

Heat Problems Grow With FinFETs, 3D-ICs
By Ann Mutschler - 13 Feb, 2014 - Comments: 2

From high-end consumer devices to rack-mounted arrays inside of data centers, thermal issues are becoming more serious—and getting much more attention. Driving this shift is the move from single chips to 3D ICs, whether they are interposer-based or stacked die. It’s a well-understood challenge: Die stacking can cause thermal issues because of the lack of a readily accessible thermal diss... » read more

Blog Review: Dec. 11
By Ed Sperling - 11 Dec, 2013 - Comments: 0

Synopsys’ Brent Gregory has developed a career growth checklist for computer science majors. They should hang this in the hallway at universities. Cadence’s Brian Fuller interviews Saar Drimer, a UK hardware engineer who has been experimenting with odd-shaped PCBs. According to Drimer, 45-degree angles aren’t always optimal. But what happens to all the expensive tools everyone has bee... » read more

Power And Signal Line Electro-migration Design And Reliability Validation Challenges For The 28nm Era
By Various Writers - 06 Dec, 2013 - Comments: 0

Reliability verification is an important aspect in the design and development of an integrated circuit (IC) to help guarantee its continued functionality over years of production use. One critical area of reliability verification is the electro-migration check analysis to ensure that the wires and vias used to connect the various devices in the chip do not fail from years of continuous use. ... » read more

How Reliable Are Interconnects In 16nm FinFET Designs?
By Arvind Vel - 05 Dec, 2013 - Comments: 0

The 16nm FinFET process node is rapidly becoming the preferred choice for advanced Integrated Circuit (IC) designs. The 16nm node’s lower standby leakage characteristics and increased drive strength capability enable IC designers to push the boundaries of low power – high performance designs. However, the choice of the node is also accompanied by reduced reliability margins, requiring desig... » read more

Paving The Way To 16/14nm
By Ed Sperling - 07 Nov, 2013 - Comments: 0

The move to the next stop on the Moore’s Law road map isn’t getting any less expensive or easier, but it is becoming more predictable. Tools and programs are being expanded to address physical effects such as electrostatic discharge (ESD), electromigration and thermal effects from increased current density. Any or all of these three checklist items can affect the reliability of a chip. A... » read more

The Week In Review: Oct. 18
By Mark LaPedus - 18 Oct, 2013 - Comments: 0

By Mark LaPedus & Ed Sperling The problems continue with extreme ultraviolet (EUV) lithography. ASML promised to deliver an 80 Watt power source by year’s end. Now, the company said it only will have a 70 Watt source by mid-2014. “We are focusing on reaching the 70 Watts by the middle of next year,” said Peter Wennink, ASML’s CEO, in a conference call to discuss the company’s res... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy