tag: electromigration

Blog Review: Dec. 11
By Ed Sperling - 11 Dec, 2013 - Comments: 0

Synopsys’ Brent Gregory has developed a career growth checklist for computer science majors. They should hang this in the hallway at universities. Cadence’s Brian Fuller interviews Saar Drimer, a UK hardware engineer who has been experimenting with odd-shaped PCBs. According to Drimer, 45-degree angles aren’t always optimal. But what happens to all the expensive tools everyone has bee... » read more

Power And Signal Line Electro-migration Design And Reliability Validation Challenges For The 28nm Era
By Various Writers - 06 Dec, 2013 - Comments: 0

Reliability verification is an important aspect in the design and development of an integrated circuit (IC) to help guarantee its continued functionality over years of production use. One critical area of reliability verification is the electro-migration check analysis to ensure that the wires and vias used to connect the various devices in the chip do not fail from years of continuous use. ... » read more

How Reliable Are Interconnects In 16nm FinFET Designs?
By Arvind Vel - 05 Dec, 2013 - Comments: 0

The 16nm FinFET process node is rapidly becoming the preferred choice for advanced Integrated Circuit (IC) designs. The 16nm node’s lower standby leakage characteristics and increased drive strength capability enable IC designers to push the boundaries of low power – high performance designs. However, the choice of the node is also accompanied by reduced reliability margins, requiring desig... » read more

Paving The Way To 16/14nm
By Ed Sperling - 07 Nov, 2013 - Comments: 0

The move to the next stop on the Moore’s Law road map isn’t getting any less expensive or easier, but it is becoming more predictable. Tools and programs are being expanded to address physical effects such as electrostatic discharge (ESD), electromigration and thermal effects from increased current density. Any or all of these three checklist items can affect the reliability of a chip. A... » read more

The Week In Review: Oct. 18
By Mark LaPedus - 18 Oct, 2013 - Comments: 0

By Mark LaPedus & Ed Sperling The problems continue with extreme ultraviolet (EUV) lithography. ASML promised to deliver an 80 Watt power source by year’s end. Now, the company said it only will have a 70 Watt source by mid-2014. “We are focusing on reaching the 70 Watts by the middle of next year,” said Peter Wennink, ASML’s CEO, in a conference call to discuss the company’s res... » read more

The Brave New World Of FinFETs
By Ed Sperling - 10 Oct, 2013 - Comments: 0

SoCs using 16nm and 14nm finFETs are expected to begin rolling out next year using a 20nm back-end-of-line process. While the initial performance and power numbers are looking very promising, the challenges of designing and building these complex chips are daunting—and there are more problems on the way. First, the good news. Initial results from foundries show a 150% improvement in perfor... » read more

Aging: Not Always A Bad Thing
By Ann Mutschler - 22 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler When IC devices are produced and shipped to end customers, it is important that they will function as specified in the application environment. Determining how a device will operate over time is a key aspect of overall reliability and is commonly referred to as ‘aging.’ Aging of electronics is not a new problem. In fact, analog and automotive designers have bee... » read more

EM Analysis At Advanced Nodes
By Valeriy Sukharev - 26 Jul, 2013 - Comments: 0

Going forward, a very different method of EM assessment can be proposed if we look at interconnect reliability from the position of its functionality, when the failure of the interconnect means its inability to function properly. The two most important functions of the chip interconnect are: Providing connectivity between different parts of design for proper signal propagations (signal circ... » read more

Experts At The Table: Who Pays For Low Power?
By Ed Sperling - 19 Jul, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the cost of low power with Fadi Gebara, research staff member for IBM’s Austin Research Lab; David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Aveek Sarkar, vice president of product engineering and support at Apache Design; and Tim Whitfield, director o... » read more

EM Analysis At Advanced Nodes
By Valeriy Sukharev - 19 Jul, 2013 - Comments: 0

EM statistics Almost 50 years ago, James Black demonstrated experimentally that TTF of the metal line stressed by direct current (DC) of density j at the temperature T follows the dependency where k is the Boltzmann constant, and A is the proportionality coefficient, which can depend on line geometry, residual stress, and temperature. Two critical parameters, the current density exponen... » read more

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