Mixed Outlook For Silicon Wafer Biz

By Mark LaPedus - 21 Feb, 2019 - Comments: 0

After a period of record growth, the silicon wafer industry is off to a slow start in 2019 and facing a mixed outlook. Generally, 200mm silicon wafer supply remains tight. But demand for 300mm silicon wafers is cooling off in some segments, causing supply to move toward equilibrium after a period of shortages. On average, though, silicon wafer prices continue to rise despite the slowdown. ... » read more

Variation At 10/7nm

By Ed Sperling - 18 Oct, 2018 - Comments: 1

Klaus Schuegraf, vice president of new products and solutions at PDF Solutions, explains why variability is a growing challenge at advanced nodes, why middle of line is now one of the big problem areas, and what happens when a via is misaligned due to a small process variation. https://youtu.be/jQfggOnxZJQ » read more

Where Is Selective Deposition?

By Mark LaPedus - 25 Jun, 2018 - Comments: 4

For years, the industry has been working on an advanced technology called area-selective deposition for chip production at 5nm and beyond. Area-selective deposition, an advanced self-aligned patterning technique, is still in R&D amid a slew of challenges with the technology. But the more advanced forms of technology are beginning to make some progress, possibly inching closer from the la... » read more

More Lithography/Mask Challenges (Part 2)

By Mark LaPedus - 17 Apr, 2018 - Comments: 3

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; Regina Freed, managing director of patterning technology at [getentity id="... » read more

Tech Talk: 5/3nm Parasitics

By Ed Sperling - 22 Feb, 2018 - Comments: 0

Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs. https://youtu.be/24C6byQBkuI » read more

Integrated Photonics (Part 2)

By Brian Bailey - 06 Sep, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss the status of integrated photonics with Twan Korthorst, CEO for PhoeniX Software; Gilles Lamant, distinguished engineer for [getentity id="22032" e_name="Cadence"]; Bill De Vries, director of marketing for Lumerical Solutions; and Brett Attaway, director of EPDA solutions at AIM Photonics, SUNY Polytechnic Institute. What follows are excerpts of tha... » read more

What Happened To DSA?

By Mark LaPedus - 19 May, 2016 - Comments: 2

Directed self-assembly (DSA) was until recently a rising star in the next-generation lithography (NGL) landscape, but the technology has recently lost some of its luster, if not its momentum. So what happened? Nearly five years ago, an obscure patterning technology called [gettech id="31046" t_name="DSA"] burst onto the scene and began to generate momentum in the industry. At about that t... » read more

The Internet Of Power Also Benefits From Moore’s Law

By Imec - 21 Jan, 2016 - Comments: 0

By Jef Poortmans It may sound strange, but striving to achieve smaller dimensions with Moore’s Law is an important enabler for producing increasingly better solar cells, with a more elaborate technology toolbox (including ALD, epitaxy, etc.) Improved process steps are constantly being developed to achieve these small transistor dimensions (for growing material layers or to etch away str... » read more

A Semiconductor Approach To Desalination

By Jim Hogan - 05 Nov, 2015 - Comments: 0

By Bernard Murphy and Jim Hogan We’re not offering breaking news when we observe that the semiconductor industry is in flux. Major consolidations and lack of funding for startups point to an industry that, outside China, is maturing and seems to have lost the recipe for rapid growth. Apologists will argue that analog or MEMS or some other domains are still strong, but this misses the point... » read more

Increasing Challenges At Advanced Nodes

By Ed Sperling - 22 Oct, 2015 - Comments: 1

Gary Patton, chief technology officer at GlobalFoundries, sat down with Semiconductor Engineering to talk about new materials, stacked die, how far FD-SOI can be extended, and new directions for interconnects and transistors. What follows are excerpts of that conversation. SE: Where do you see problems at future nodes? Patton: At the device level, we have to be able to pattern these thing... » read more

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Knowledge Centers
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