tag: epitaxy

Manufacturing Of Next-Generation Channel Materials
By Michael Watts - 05 Oct, 2015 - Comments: 0

One of the many challenges for the IC developers is to change the channel material to increase transistor mobility. But what about manufacturing? Can LED-style epitaxy be migrated to high-volume silicon manufacturing? “The use of Ge and InGaAs quantum wells is an extension of the current strained Si strategy," said Aaron Thean, vice president of process technologies and director of the log... » read more

Still Waiting For III-V Chips
By Mark LaPedus - 19 Feb, 2015 - Comments: 0

For years, chipmakers have been searching for an alternative material to replace traditional silicon in the channel for advanced CMOS devices at 7nm and beyond. There’s a good reason, too: At 7nm, silicon will likely run out of steam in the channel. Until recently, chipmakers were counting on III-V materials for the channels, at least for NFET. Compared to silicon, III-V materials provide ... » read more

Counting And Controlling DSA Defects
By Katherine Derbyshire - 13 Nov, 2014 - Comments: 1

If directed self-assembly is to succeed in semiconductor manufacturing, [gettech id="31046" t_name="DSA"] processes must achieve defect rates in line with the stringent requirements of sub-20nm device nodes. So far, they haven’t. However, it’s not yet clear whether the high defect rates represent a real obstacle, or are simply part of the development of any new, immature process technology... » read more

More Problems Ahead
By Ed Sperling - 25 Aug, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss future scaling problems with Lars Liebmann, a fellow at IBM; Adam Brand, managing director of transistor technology at Applied Materials; Karim Arabi, vice president of engineering at Qualcomm; and Srinivas Banna, a fellow for advanced technology architecture at GlobalFoundries. SE: There seems to be some debate in this group about whether we’r... » read more

Germanium wedge-FETs pry away misfit dislocations
By Katherine Derbyshire - 23 Jan, 2014 - Comments: 1

Any approach to alternative channel integration must consider the lattice mismatch between silicon and other channel materials. Some schemes, such as IMEC’s selective epitaxy, view the lattice mismatch as an obstacle and look for ways to minimize its effects. This point of view certainly has merit: misfit dislocations do significantly degrade transistor performance. Still, back in 2011 Shu-Ha... » read more

Alternative Channel Materials For Post-Silicon FinFETs
By Katherine Derbyshire - 16 Dec, 2013 - Comments: 4

At first glance, other semiconductors always have looked more attractive to device designers than silicon. Both germanium and III-V compound semiconductors have higher carrier mobility, allowing faster switching at the same device size. And yet, as manufacturers begin to consider alternative channel materials for sub-10nm devices, the industry is remembering why silicon became a standard in ... » read more

It’s A Materials World
By Mark LaPedus - 15 Aug, 2013 - Comments: 0

By Mark LaPedus At a recent event, Intel’s fab materials guru described a nightmarish occurrence that nearly brought the chip giant to its knees. Tim Hendry, director of fab materials and vice president of the Technology and Manufacturing Group at Intel, said the company obtained a critical material from an undisclosed supplier. “This large sub-supplier, a very large chemical company, m... » read more

Mobility Gets A Boost With Expanded Epi Applications
By Applied Materials Writers - 17 Jul, 2013 - Comments: 0

By Jeremy Zelenko Even as industry moves into the era of the high k metal gate (HKMG) and FinFET transistor, chipmakers continue to seek ways to improve device performance. One of the latest advances and the subject of an Applied Materials announcement made today is to extend epitaxial deposition from PMOS to NMOS transistors. Implementing an NMOS epitaxy (epi) process in addition to the estab... » read more

The Week In Review: July 15
By Mark LaPedus - 15 Jul, 2013 - Comments: 0

By Mark LaPedus There are more problems surfacing with extreme ultraviolet (EUV) lithography. Yes, the light source remains a problem, but the resists appear to be in decent shape. “The next challenge is the mask blank,” said Stefan Wurm, director of Sematech’s lithography program. The new problem involves ion beam deposition, which apparently is causing defects and overfill on EUV masks... » read more

Speeding Up NMOS
By Ed Sperling - 08 Jul, 2013 - Comments: 0

By Ed Sperling For years—decades, in fact—the NMOS transistor world has been on cruise control. NMOS is naturally faster and its performance has scaled better than PMOS. PMOS has had a cost advantage. But lately, it has been catching up in performance, too. In fact, at 20nm the two transistor types have proven nearly equal in performance—but not for long. NMOS is about to get a big bo... » read more

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