tag: ESD Alliance

DAC’s Passageway To Design Infrastructure
By Bob Smith - 06 Feb, 2018 - Comments: 0

This year's Design Automation Conference will include an "alley" on the exhibit floor, but it won't be a dark, narrow passageway we think of when we hear "alley." Instead, the new Design Infrastructure Alley will be a well-illuminated tribute to the design technology infrastructure, a fundamental element for the creation and design of complex electronic systems and components. The Design Inf... » read more

The Week In Review: Design
By Jesse Allen - 02 Feb, 2018 - Comments: 0

Startups Two new companies unveiled this week – Metrics Technologies and Movellus. Metrics Technologies is providing a Software-as-a-Service SystemVerilog simulator and verification manager that are available as pay-per-minute. This allows companies to have fully elastic system capabilities to accommodate peak simulation demand. “Cloud technology and Software as a Service business mo... » read more

The Week In Review: Design
By Jesse Allen - 26 Jan, 2018 - Comments: 0

Security Addressing the Meltdown and Spectre speculative execution vulnerabilities has not gone smoothly. Intel's firmware update caused unexpected behavior and a higher than expected number of reboots for its Haswell and Broadwell chips, leading the company to recommend users stop patching until an updated version of the patch is available. Microsoft's attempts to fix the issue left some W... » read more

Predictions: Methodologies And Tools
By Brian Bailey - 25 Jan, 2018 - Comments: 0

Predictions are divided into four posts this year. Part one covered markets and drivers. The second part looked at manufacturing, devices and companies and this part will cover methodologies and tools. In addition, the outlook from EDA executives will be provided in a separate post. Intellectual property As designs get larger, it should be no surprise that the size of the [getkc id="43" kc_... » read more

The Week In Review: Design
By Jesse Allen - 19 Jan, 2018 - Comments: 0

M&A Barco Silex, now named Silex Inside, split from parent company Barco in a management buyout in partnership with a group of private investors lead by Dutch investment company Vehold BV. The company will continue its focus on security, video compression, and interface IP, along with design services. Tools & IP Mentor is making a version of its HyperLynx design rule checking tool ... » read more

EDA, IP Sales Up 8%
By Ed Sperling - 15 Jan, 2018 - Comments: 0

The EDA sector continues to exhibit solid growth, increasing 8% to $2.2262 billion in Q3, up from $2.0937 billion in the same period in 2016, according to the most recent stats from the ESD Alliance Market Statistics Service. The four-quarter moving average was up 11.5%, year over year. While all of the numbers were up, two areas showed extraordinary growth. One involved Japan, which showed ... » read more

Reflection On 2017: Design And EDA
By Brian Bailey - 03 Jan, 2018 - Comments: 0

People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. We see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but most have this year. (Part one looked at the predictions associated with s... » read more

Women In Power
By Ann Mutschler - 01 Dec, 2017 - Comments: 0

This is not my usual, technically-focused report, but it's important sometimes to reflect on the human side of the industry, which can seem woefully absent at times in the scramble to get projects out the door and meet quarterly numbers. This past Tuesday, November 28, I moderated a panel of women who are truly inspirational for the achievements in their respective parts of the industry, an... » read more

The Week In Review: Design
By Jesse Allen - 01 Dec, 2017 - Comments: 0

Tools Imperas debuted its RISC-V Processor Developer Suite, a set of models, a software simulator, and tools to validate, verify, and provide early estimation of timing performance and power consumption for RISC-V processors. IP Minima Processor revealed its dynamic-margining subsystem IP for near-threshold voltage design. The startup's hardware and software IP works with a CPU or DSP proc... » read more

The Week In Review: Design
By Jesse Allen - 17 Nov, 2017 - Comments: 0

Tools Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include improved performance when using code containing many inline randomized calls and up to 29% faster simulation speed of UVM. Pulsic added new features to its Unity Bus Planner for planning... » read more

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