The Week In Review: Design

Meltdown, Spectre tough to tackle; tools for RISC-V; power models; GDDR6; automotive GPU.

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Security
Addressing the Meltdown and Spectre speculative execution vulnerabilities has not gone smoothly.

Intel’s firmware update caused unexpected behavior and a higher than expected number of reboots for its Haswell and Broadwell chips, leading the company to recommend users stop patching until an updated version of the patch is available. Microsoft’s attempts to fix the issue left some Windows AMD systems unbootable (the issue is now resolved) and some Windows patches were prevented from running by third-party antivirus software. Meanwhile, Andes Technology says none of its processors are affected by either Meltdown or Spectre due to a difference in processor pipeline design.

A list of links to official advisories is available from the Meltdown/Spectre info site.

Tools
UltraSoC released a RISC-V processor trace solution with options ranging from a lightweight package that combines simple run-control with USB as the debug interface to more sophisticated solutions with both run control and trace, and interfacing via either JTAG or UltraSoC’s non-intrusive, bare-metal USB. The trace encoder supports both 32 and 64-bit RISC-V designs.

Codasip launched the latest version of its IP design and customization software for configuration and optimization of RISC-V processors. Updates to Studio 7 include native support for AMBA interfaces, IEEE 1149-7-compatible 2-wire JTAG to minimize pin-count, and improvements in clock-gating for low-power requirements.

IP
Micron, Rambus, Northwest Logic, and Avery Design Systems teamed up on a GDDR6 platform complete with memory, PHY, controller and verification IP. The chip uses BGA packaging with target speed up to 64GB/s. Along with the announcement, Rambus debuted its GDDR6 PHY.

Imagination debuted a new high-performance GPU core supporting multiple ultra-high resolution displays for automotive cluster, Head-Up Display (HUD) and infotainment. The four-cluster PowerVR Series8XT GT8540 GPU can simultaneously drive up to six 4K screens with complex UIs at 60fps. Hardware virtualization allows for separation of services and applications, supporting up to eight applications or services running in separate containers at once.

Imagination also announced an SDK for developing neural network applications on PowerVR GPUs. Both an API and SDK are included, as well as an image for flashing on to an Acer Chromebook R13 for hardware development.

SoC-e’s latest release of its Managed Ethernet Switch IP core supports Device Level Ring (DLR), a Layer-2 protocol that provides media redundancy in a ring topology. The IP Core allows for implementation of a DLR end-device with embedded switching capabilities and supports multiple Ethernet interfaces.

Deals
Flex Logix’s EFLX platform was selected by HiPer, a consortium of Israeli semiconductor and systems companies including Mellanox, Satixfy, DSP Group, and AutoTalks, which will use it to design an architecture and technology 16nm evaluation chip. Bar Ilan University’s SoC Lab will prove out and implement a chip that can be used by each member company.

Starblaze Technology licensed Moortec’s 28nm Temperature Sensor IP in its STAR1000 high-end consumer and starter enterprise SSD controller, citing high accuracy and ease of integration.

Renesas deployed Synopsys’ DFTMAX LogicBIST on a mixed-signal, large scale integration design to meet automotive safety integrity levels. The companies certified DFTMAX LogicBIST according to Part 8 of the ISO 26262 functional safety standard, enabling deployment on automotive designs.

Marvell signed a patent license agreement with Rambus, giving the company access to Rambus’ memory controller, SerDes and security technologies.

Minima Processor, a startup providing near-threshold voltage design technology including dynamic margining and ultra-wide DVFS, joined the ESD Alliance.

Standards
Si2 announced a new System Level Power working group to create the Si2 Unified Power Model (UPM), a standard for power management in system-level IC design. A key goal of the group is creation of a single model to represent power data at the system level across a range of process, voltage, and temperature (PVT) points and include the capability to supply power data to IEEE 1801/UPF power state models. Ansys, Cadence, IBM, Intel, and Entasys are working group members.

Numbers
IC Insights predicts semiconductor unit shipments to climb to 1,075.1 billion in 2018, for 9% growth for the year. Opto, sensor, and discrete devices are forecast to account for 70% of total units, with ICs making up the remaining 30%. For ICs, fast-growing areas are expected to include application-specific analog, special purpose logic, and 32-bit MCUs.

Eta Compute completed an $8 million Series A round of financing led by Walden International with additional participation from Acorn Pacific Ventures and Walden Riverwood Ventures. The startup focuses on low power processor IP designed for machine learning tasks based on spiking neural networks.

Events
DesignCon: Jan. 30-Feb. 1 in Santa Clara, CA. The high-speed boards conference and expo features a keynote panel on the SI/PI & EMI forecast for the next five years, plus a keynote presentation on autonomous vehicle safety and another on piloting the next space mission past Pluto. The conference includes three all-day training sessions focused on signal integrity, differential signaling, and test and measurement techniques.

Phil Kaufman Award Ceremony: Feb. 8 in San Jose, CA. Dr. Rob A. Rutenbar, senior vice chancellor for Research at the University of Pittsburgh, will be presented the 2017 Phil Kaufman Award for his contributions to algorithms and tools for analog and mixed-signal designs.

FPGA 2018: Feb. 25-27 in Monterey, CA. The conference includes a workshop on packet processing with the P4 language, a panel and several presentations focused on machine learning, and a look at new architectures.

DVCon 2018: Feb. 26-Mar. 1 in San Jose, CA. Features include tutorials on the Portable Stimulus Standard and UVM, a keynote on how new segments in the industry are changing verification, and a new slate of short workshops. Brian Bailey takes a look at what to check out. Early registration ends today, Jan. 26.

DAC 2018: June 24-28 in San Francisco, CA. DAC is bringing back the Silicon and Technology Art Show this year to showcase the beauty of electronic devices. Submissions are due April 15. Plus, nominations are now open for the Marie R. Pistilli Women in EDA award, with nominations open through March 2. Additionally, a new area of DAC will focus on design and IT infrastructure and feature presentations and exhibits on the management of computing resources and hardware and software products and services.



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