Blog Review: Sept. 21

By Jesse Allen - 21 Sep, 2022 - Comments: 0

Arm's Neil Burgess and Sangwon Ha explain why they've joined Intel and Nvidia in proposing a new 8-bit floating point specification to enable neural network models developed on one platform to be run on other platforms without encountering the overhead of having to convert the vast amounts of model data between formats while reducing task loss to a minimum. Synopsys' Manuel Mota examines ver... » read more

Blog Review: Sept. 14

By Jesse Allen - 14 Sep, 2022 - Comments: 0

Synopsys' Godwin Maben, Piyush Sancheti, and Hany Elhak examine some of the top chip design considerations for medical devices and why they require careful analysis of power to reduce the number surgeries to replace batteries, reliability for devices that can be expected to last for ten years or more, and security to protect private medical data and prevent breaches. Siemens' Chris Spear exp... » read more

Blog Review: Aug. 10

By Jesse Allen - 10 Aug, 2022 - Comments: 0

Siemens' Heather George provides a primer on 3D IC, including the problems it is trying to solve, what differentiates it from other multi-chip technologies, and some of the unique challenges in 3D integration. Cadence's Paul McLellan shares highlights from the Automobil Elektronik Kongress, including how the increasing amount of software in a car is driving disruption in the automotive suppl... » read more

Blog Review: July 27

By Jesse Allen - 27 Jul, 2022 - Comments: 0

Siemens' Keith Felton expects a greater emphasis on several areas of semiconductor package design next year, including accelerated growth of heterogeneous integration, multiple die, and chiplet SiPs, emergence and adoption of organic-based interposers, and early detection of thermal and electromechanical issues. Cadence's Paul McLellan visits Imec to find out about getting the heat out of 3D... » read more

Week In Review: Design, Low Power

By Jesse Allen - 15 Jul, 2022 - Comments: 0

Tools & IP Cadence will acquire Future Facilities, a provider of electronics cooling analysis and energy performance optimization solutions for data center design and operations using physics-based 3D digital twins. Future Facilities’ product portfolio includes an electronics thermal solution, as well as computational fluid dynamics (CFD) electronics cooling simulation technology that op... » read more

Blog Review: July 13

By Jesse Allen - 13 Jul, 2022 - Comments: 0

Siemens' John Sturtevant finds that the patterning requirements of next generation lithographic processes have pushed lithographers to explore the advantages of curvilinear masks, and notes some of the tools coming along to help. Cadence's Paul McLellan learns from Kyle Chen of Microsoft and Suomin Cui of Cadence how deep learning and electromagnetic solvers can be used to optimize high-dens... » read more

Who Benefits From Chiplets, And When

By Ed Sperling - 31 May, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss new packaging approaches and integration issues with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front of a... » read more

Blog Review: April 27

By Jesse Allen - 27 Apr, 2022 - Comments: 0

Siemens' Joseph Dailey and Jake Wiltgen dispel misunderstandings around safety qualification of software tools and point to some of the safety issues that could lead to schedule delays and additional costs. Synopsys' Mark Kahan explains the testing that went into creating parts of the James Webb Space Telescope and key questions that were asked to ensure the mission could be successful even ... » read more

Mask And Metrology Technology Trends

By Bob Smith - 21 Apr, 2022 - Comments: 0

Aselta Nanographics of Grenoble, France, which produces software for wafer and mask patterning based on e-beam technology for IC manufacturing, along with advanced metrology solutions for scanning electron microscopes, recently became an ESD Alliance member. Adding to its impressive credentials, Aselta is a spin-off of CEA-Leti, the electronics and information technologies research institut... » read more

Blog Review: April 20

By Jesse Allen - 20 Apr, 2022 - Comments: 0

Cadence's Paul McLellan looks at the difference between 3D packaging and 3D integration and the different approaches to system-in-package designs. Siemens' Spencer Acain finds that despite having less precision and flexibility than digital chips, analog computing is having a resurgence in the space of cutting-edge AI thanks to the speed and energy efficiency in specialized tasks. Synopsys... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: ESD Alliance