Ensuring ESD Protection Verification With Industry-Standard Checks

By Mark Tawfik - 21 Dec, 2022 - Comments: 0

Electronic design automation (EDA) verification of electrostatic discharge (ESD) protection is a complex task. Different integrated circuit (IC) design companies use different ESD protection approaches, different design flows, and different verification tools. To establish a consistent and comprehensive ESD EDA verification flow, the ESD Association (ESDA) provides recommended ESD compliance ch... » read more

Are You Paying Proper Attention To Your ESD Design Windows?

By Derong Yan - 10 Nov, 2022 - Comments: 0

Electrostatic discharge (ESD) issues in integrated circuit (IC) chip designs have become more critical at advanced semiconductor process nodes, due to shrinking transistor dimensions and oxide layer thickness [1]. There are many ESD design rules and flows that designers check for common ESD issues, such as topological checks for the existence of ESD protection devices, current density (CD) chec... » read more

Complete Reliability Verification For Multiple-Power-Domain Designs

By Siemens EDA - 09 Nov, 2022 - Comments: 0

With increasing design complexity and a heightened focus on reliability at all levels of integrated circuit (IC) design from intellectual property (IP) to full-chip, accurate and full verification coverage of the different reliability concerns within an IC design is essential. Designs containing multiple power domains add more complexity to reliability verification with the need to validate int... » read more

2.5/3D IC Reliability Verification Has Come A Long Way

By Dina Medhat - 01 Aug, 2022 - Comments: 0

2.5D/3D integrated circuits (ICs) have evolved into an innovative solution for many IC design and integration challenges. As shown in figure 1, 2.5D ICs have multiple dies placed side-by-side on a passive silicon interposer. The interposer is placed on a ball grid array (BGA) organic substrate. Micro-bumps attach each die to the interposer, and flip-chip (C4) bumps attach the interposer to the ... » read more

Design & Implementation of CMOS Interface Circuits For high-Voltage Automotive Signals, with Fully Integrated Clamps

By Technical Paper Link - 30 May, 2022 - Comments: 0

Research paper titled "CMOS Interface Circuits for High-Voltage Automotive Signals" from University of Parma and Silis s.r.l. Abstract "The acquisition of high-voltage signals from sensors and actuators in an internal-combustion engine is often required for diagnostic purposes or in the case of conversion to alternative fuels, such as hydrogen, natural gas, or biogas. The integration of ele... » read more

Context-Aware SPICE Simulation Improves The Fidelity Of ESD Analysis

By Neel Natekar - 10 Feb, 2022 - Comments: 0

Electrostatic discharge (ESD) is a major reliability concern for integrated circuit (IC) designs. ESD verification is proving to be a significant challenge at advanced nodes, due to growing IC design complexity and transistor counts. Traditional ESD verification approaches using parasitic extraction followed by SPICE simulation are deficient in providing simulation results in a practical runtim... » read more

Can We Efficiently Automate 2.5/3D IC ESD Protection Verification?

By Dina Medhat - 23 Sep, 2021 - Comments: 0

Protection against ESD events (commonly referred to as ESD robustness) is an extremely important aspect of integrated circuit (IC) design and verification, including 2.5/3D designs. ESD events cause severe damage to ICs due to a sudden and unexpected flow of electrical current between two electrically charged objects. This current may be caused by contact, an electrical short, or dielectric bre... » read more

Automated ESD Protection Verification For 2.5D And 3D ICs

By Siemens EDA - 22 Sep, 2021 - Comments: 0

While automated flows for ESD protection verification are well-established for 2D ICs, 2.5D and 3D designs present new challenges in both ESD circuit design and verification. Advanced automated ESD verification methodology accurately and effectively evaluates ESD protection in 2.5/3D IC designs. Ensuring correct and consistent ESD protection in 2.5/3D ICs raises the reliability and product life... » read more

The Shortest Path Deception

By Derong Yan - 09 Sep, 2021 - Comments: 1

When manufacturing, assembling, and using integrated circuit (IC) chips, the electrostatic discharge (ESD) caused by accumulated static can damage the IC circuitry if the circuit is not properly protected [1]. To prevent such damage, ESD protection devices are designed into the circuitry such that they will create a low impedance path that limits the peak voltage and current by diverting excess... » read more

Shortest Resistance Path Deception In ESD Protection Circuit P2P Debug

By Siemens EDA - 08 Sep, 2021 - Comments: 1

Verifying and fixing ESD protection circuit violations is an essential step in tapeout sign-off flows for today’s IC chip designs. As one of the most commonly used ESD verification flows, the point to point (P2P) flow checks the resistances of ESD discharge paths in layout designs to ensure they are within design thresholds. However, when debugging P2P violations, information such as the shor... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

Defining The Chiplet Socket

The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?

by Brian Bailey

tag: ESD

Ensuring ESD Protection Verification With Industry-Standard Checks

Are You Paying Proper Attention To Your ESD Design Windows?

Complete Reliability Verification For Multiple-Power-Domain Designs

2.5/3D IC Reliability Verification Has Come A Long Way

Design & Implementation of CMOS Interface Circuits For high-Voltage Automotive Signals, with Fully Integrated Clamps

Context-Aware SPICE Simulation Improves The Fidelity Of ESD Analysis

Can We Efficiently Automate 2.5/3D IC ESD Protection Verification?

Automated ESD Protection Verification For 2.5D And 3D ICs

The Shortest Path Deception

Shortest Resistance Path Deception In ESD Protection Circuit P2P Debug

Trending Articles

NAND Flash Targets 1,000 Layers

Testing For Thermal Issues Becomes More Difficult

Auto Chip Aging Accelerates In Hot Climates

Is In-Memory Compute Still Alive?

Baby Steps Toward 3D DRAM

Knowledge Centers
Entities, people and technologies explored