Tech Talk: 5/3nm Parasitics

By Ed Sperling - 22 Feb, 2018 - Comments: 0

Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs. https://youtu.be/24C6byQBkuI » read more

New Nodes, Materials, Memories

By Ed Sperling - 15 Feb, 2018 - Comments: 0

Ellie Yieh, vice president and general manager of Advanced Product Technology Development at [getentity id="22817" e_name="Applied Materials"], and head of the company's Maydan Technology Center, sat down with Semiconductor Engineering to talk about challenges, changes and solutions at advanced nodes and with new applications. What follows are excerpts of that conversation. SE: How far can w... » read more

The Next 5 Years Of Chip Technology

By Ed Sperling - 15 Jan, 2018 - Comments: 1

Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of [getentity id="22820" comment="Lam Research"]; Mark Dougherty, vice president of advanced module engineering at [getentity id="22819" comment="GlobalFoundries"]; David Shortt, technical fellow at [getentity id="22876" co... » read more

The Next 5 Years Of Chip Technology

By Ed Sperling - 18 Dec, 2017 - Comments: 0

Is 7nm The Last Major Node?

By Ed Sperling - 20 Jul, 2017 - Comments: 3

A growing number of design and manufacturing issues are prompting questions about what scaling will really look like beyond 10/7nm, how many companies will be involved, and which markets they will address. At the very least, node migrations will go horizontally before proceeding numerically. There are expected to be more significant improvements at 7nm than at any previous node, so rather th... » read more

New BEOL/MOL Breakthroughs?

By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

Following Multiple Patterns

By Mark LaPedus - 16 Mar, 2017 - Comments: 2

The lithography market is in flux. Today, chipmakers plan to extend today’s 193nm immersion lithography and multi-patterning to at least 10nm and 7nm. For the most critical layers, though, it’s unclear if optical lithography can extend beyond 7nm. For that reason, chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm. To get a handle on the state of patterning, S... » read more

TFETs Cut Sub-Threshold Swing

By Katherine Derbyshire - 16 Mar, 2017 - Comments: 0

One of the main obstacles to continued transistor scaling is power consumption. As gate length decreases, the sub-threshold swing (SS) — the gate voltage required to change the drain current by one order of magnitude — increases. As Qin Zhang, Wei Zhao, and Alan Seabaugh of Notre Dame explained in 2006, SS faces a theoretical minimum of 60 mV/decade at room temperature in conventional MO... » read more

New Techniques To Analyze And Reduce Etch Variation

By Coventor - 25 Jan, 2017 - Comments: 1

Time division multiplex (TDM) plasma etch processes (commonly referred to as Deep Reactive ION Etching [“DRIE”]) use alternating deposition and etch steps cyclically to produce high aspect ratio structures on a silicon substrate. These etch processes have been widely applied in the manufacturing of silicon MEMS devices, and more recently in creating through silicon vias in 3D silicon struct... » read more

Etching Technology Advances

By Jeff Dorsch - 15 Dec, 2016 - Comments: 0

Let’s get really, really small. That directive from leading semiconductor companies and their customers is forcing the whole semiconductor supply chain to come up with new ways to design and manufacture ever-shrinking dimensions for chips. The current push is to 10nm and 7nm, but R&D into 5nm and 3nm is already underway. To put this in perspective, there are roughly two silicon atom... » read more

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tag: etch

Tech Talk: 5/3nm Parasitics

New Nodes, Materials, Memories

The Next 5 Years Of Chip Technology

The Next 5 Years Of Chip Technology

Is 7nm The Last Major Node?

New BEOL/MOL Breakthroughs?

Following Multiple Patterns

TFETs Cut Sub-Threshold Swing

New Techniques To Analyze And Reduce Etch Variation

Etching Technology Advances

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