tag: failure analysis

SEM Analysis Reveals Real Cause Of Chip Failure
By DELTA, a part of FORCE Technology - 08 Jul, 2019 - Comments: 0

When it comes to ASIC design, DELTA’s motto is “first time right”. When the first wafers from the wafer fab showed severe electrical malfunction, we were extremely frustrated. To investigate the failure, the design team started electrical characterization of prototypes. Overall, a short between power and ground was observed and furthermore RF inputs exhibited strange VI characteristics. T... » read more

Failure Analysis Of Electronic Devices Using Scanning Acoustic Microscopy
By Yavuz Kose - 11 Jun, 2019 - Comments: 0

Scanning acoustic microscopy, or SAM, is a non-destructive technique used in failure analysis of complex devices. SAM can provide a resolution down to sub-micron thicknesses. SAM is an efficient tool for analysis of adhesion between layers and presence of possible flaws in each layer. This can be used e.g. for investigations of sealing, coating, flip-chip underfills, BGA, QFN, wafer to wafer ... » read more

Breakthrough For Scan Diagnosis With Machine Learning
By Matthew Knowles - 07 May, 2019 - Comments: 0

Cell-aware diagnosis is a new and effective way to detect defects inside standard cells. Industry standard failure analysis (FA) results from a major foundry show that cell-aware diagnosis is very effective at increasing the resolution of the diagnosis by reducing the number of suspects in cell-internal defect data. With advanced technology nodes, we have more complex layout structures and f... » read more

A Different Approach To Failure Analysis
By Yavuz Kose - 07 May, 2019 - Comments: 0

Decapsulation of plastic IC packages in different types and size were performed by wet chemical technique. Studied devices were to use in satellites and going to subject a series of test which require the die to be exposed. Different package types with changing sizes and bonding types such as Au- and Cu-bonded packages for unmounted and PCBA-mount components were successfully achieved. A combin... » read more

Moving Beyond Geometries: Context-Aware Verification Improves Design Quality And Reliability
By Sherif Hany - 25 Apr, 2019 - Comments: 0

Context-aware checks integrate physical and electrical information to evaluate a wide range of design conditions, from advanced design rule compliance, to circuit and reliability verification, to design optimization and finishing. Automated context-aware checking provides designers with actionable results that improve both debugging efficiency and verification precision. Introduction Many p... » read more

X-Ray Reveals Wire Bonding And Field Failures
By DELTA, a part of FORCE Technology - 09 Apr, 2019 - Comments: 0

Wire bonding is widely used for first-level interconnection of semiconductor die to component leads or pads. It is vital that the interconnection corresponds to the product-specific bonding diagram and that the wire bonding is of an acceptable robustness and quality. X-ray technology is critical for ensuring both. To read more, click here. » read more

Failure Analysis of a Product—Not Only a Component
By DELTA, a part of FORCE Technology - 12 Feb, 2019 - Comments: 0

Classic failure analysis (FA) technique generally deals with a single failed component in a complete product to detect the root cause of failure. This approach is inexpensive and less time-consuming. However, this may end up with a wrong interpretation of the product failure or overlooking the synergetic effect of different components related to the failure. This article is about a product on ... » read more

Avoiding Down Times: Monitoring, Diagnostics And Troubleshooting Of Industrial Wireless Systems
By Fraunhofer IIS/EAS - 07 Feb, 2018 - Comments: 0

The ever-growing proliferation of wireless devices and technologies used for Internet of Things (IoT) applications, such as patient monitoring, military surveillance, and industrial automation and control, has created an increasing need for methods and tools for connectivity prediction, information flow monitoring, and failure analysis to increase the dependability of the wireless network. Inde... » read more

Pattern Matching In Test And Yield Analysis
By Geir Eide - 23 Jun, 2016 - Comments: 1

By Jonathan Muirhead and Geir Eide It’s no secret that a successful yield ramp directly impacts integrated circuit (IC) product cost and time-to-market. Tools and techniques that help companies ramp to volume faster, while also reducing process and design variability, can be the difference between profit and loss in a competitive market. And while pattern matching technology has been aroun... » read more

Balancing The Cost Of Test
By Brian Bailey - 23 Oct, 2014 - Comments: 0

As semiconductor devices became larger and more complex, the cost of [getkc id="174" kc_name="test"] increased. Testers were large pieces of capital equipment designed to execute functional vectors at-speed and the technology being used had to keep up with increasing demands placed on them. Because of this, the cost of test did not decrease in the way that other high-tech equipment did. Around ... » read more

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