Advancing To The 3nm Node And Beyond: Technology, Challenges And Solutions

By Michael Hargrove - 19 Aug, 2021 - Comments: 0

It seems like yesterday that finFETs were the answer to device scaling limitations imposed by shrinking gate lengths and required electrostatics. The introduction of finFETs began at the 22nm node and has continued through the 7nm node. Beyond 7nm, it looks like nanosheet device structures will be used for at least the 5nm and probably the 3nm nodes. The nanosheet device structure is the brainc... » read more

Angstrom-Level Measurements With AFMs

By Mark LaPedus - 19 Aug, 2021 - Comments: 0

Competition is heating up in the atomic force microscopy (AFM) market, where several vendors are shipping new AFM systems that address various metrology challenges in packaging, semiconductors and other fields. AFM, a small but growing field that has been under the radar, involves a standalone system that provides surface measurements on structures down to the angstrom level. (1 angstrom = 0... » read more

Process Variation Analysis Of Device Performance Using Virtual Fabrication — Methodology Demonstrated On A CMOS 14-nm FinFET Vehicle

By Coventor - 18 Aug, 2021 - Comments: 0

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. W... » read more

Intel/GF deal: Pros, Cons, Unknowns

By Mark LaPedus - 22 Jul, 2021 - Comments: 1

The industry is still buzzing over a Wall Street Journal report that Intel is in talks to acquire GlobalFoundries (GF) for $30 billion. It’s been a week since the report appeared. Intel is still mum. GF says there are no talks taking place. Regardless, it’s worth looking at all of the possible scenarios just in case, and the pros and cons involved. There are layers upon layers of iron... » read more

In-Chip Sensing And PVT Monitoring: Not Just An Insurance Policy

By Ramsay Allen - 11 May, 2021 - Comments: 0

You wouldn’t drive an expensive car without insurance or take a flight in an aircraft without performing instrument and control surface checks. So why would you take the risk of designing a multi-million dollar advanced node semiconductor device without making sure you are aware of, and able to manage, the dynamic conditions that had the potential to make or break a silicon product? Advanced... » read more

Sensors Will Proliferate In SoCs

By Tim Penhale-Jones - 15 Oct, 2020 - Comments: 0

No one likes being put on the spot, and yet we all like a forecast…and as we all know, the only guarantee with a forecast is that it is wrong. Sports commentators have carved out a special niche for themselves with the ‘commentators curse:’ just as they extol the virtues of an individual or a team, the sporting gods prove them wrong in spectacular fashion! Governments are no better: econo... » read more

Post Layout Simulation Is Becoming The Bottleneck For Analog Verification

By Greg Curtis - 25 Jun, 2020 - Comments: 0

My, have times changed. I remember when I first started out as a green analog designer right out of college, we would cut rubylith masking film on a large light table representing the different layers of our design to generate the design for manufacturing of the chip. We proactively worked to mitigate cross coupling of noise to our signal nets, but we were rarely concerned about interconnect re... » read more

New Approaches For Dealing With Thermal Problems

By Ann Mutschler - 11 Jun, 2020 - Comments: 0

New thermal monitoring, simulation and analysis techniques are beginning to coalesce in chips developed at leading-edge nodes and in advanced packages in order to keep those devices running at optimal temperatures. This is particularly important in applications such as AI, automotive, data centers and 5G. Heat can kill a chip, but it also can cause more subtle effects such as premature aging... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 13 Mar, 2020 - Comments: 0

Market research The coronavirus is having a major impact on the semiconductor, smartphone and related markets. For example, global fab equipment spending promises to rebound from its 2019 downturn and see a modest recovery this year, according to a report from SEMI. But the coronavirus (COVID-19) outbreak has eroded fab equipment spending in China and elsewhere in 2020, according to the rep... » read more

Manufacturing Bits: Feb. 25

By Mark LaPedus - 25 Feb, 2020 - Comments: 0

Diamond finFETs HRL Laboratories has made new and significant progress to develop diamond finFETs. HRL, a joint R&D venture between Boeing and General Motors, has developed a new ohmic regrowth technique for diamond FETs. This in turn could pave the way towards commercial diamond FETs. Applications include spacecraft, satellites and systems with extreme temperatures. Still in R&D, diamo... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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