More Nodes, New Problems

By Ann Mutschler - 26 Apr, 2018 - Comments: 0

The rollout of leading-edge process nodes is accelerating rather than slowing down, defying predictions that device scaling would begin to subside due to rising costs and the increased difficulty of developing chips at those nodes. Costs are indeed rising. So are the number of design rules, which reflect skyrocketing complexity stemming from multiple patterning, more devices on a chip, and m... » read more

New Patterning Options Emerging

By Mark LaPedus - 19 Apr, 2018 - Comments: 1

Several fab tool vendors are rolling out the next wave of self-aligned patterning technologies amid the shift toward new devices at 10/7nm and beyond. Applied Materials, Lam Research and TEL are developing self-aligned technologies based on a variety of new approaches. The latest approach involves self-aligned patterning techniques with multi-color material schemes, which are designed for us... » read more

Modeling Semiconductor Process Variation

By Coventor - 19 Apr, 2018 - Comments: 0

3D semiconductors, 3D NAND Flash, FinFETS and other advanced devices are bringing tremendous opportunities to the semiconductor industry. Unfortunately, these devices are also bringing new design, process and production problems. Process variability has been a major contributor to production delays as feature sizes have decreased and process complexity has increased. Virtual fabrication is a co... » read more

Looking At Test Differently

By Ed Sperling - 05 Mar, 2018 - Comments: 1

Wilhelm Radermacher, executive advisor at [getentity id="22816" e_name="Advantest"], sat down with Semiconductor Engineering to discuss how the impact of rapid market changes, advanced packaging approaches and increasing complexity on test strategies and equipment. What follows are excerpts of that conversation. SE: As we move into new markets where use models and stresses on devices are dif... » read more

Tech Talk: 5/3nm Parasitics

By Ed Sperling - 22 Feb, 2018 - Comments: 0

Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs. https://youtu.be/24C6byQBkuI » read more

Transistor Options Beyond 3nm

By Mark LaPedus - 15 Feb, 2018 - Comments: 18

Despite a slowdown in chip scaling amid soaring costs, the industry continues to search for a new transistor type 5 to 10 years out—particularly for the 2nm and 1nm nodes. Specifically, the industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, accord... » read more

New Thermal Issues Emerge

By Ann Mutschler - 12 Feb, 2018 - Comments: 0

Thermal monitoring is becoming more critical as gate density continues to increase at each new node and as chips are developed for safety critical markets such as automotive. This may sound counterintuitive because the whole point of device scaling is to increase gate density. But at 10/7 and 7/5nm, static current leakage is becoming a bigger issue, raising questions about how long [getkc id... » read more

Tech Talk: Applying Machine Learning

By Ed Sperling - 08 Feb, 2018 - Comments: 0

Norman Chang, chief technologist at ANSYS, talks about real applications of machine learning for mechanical, fluid dynamics and chip-package-system design. https://youtu.be/MqYX0wbwSfE » read more

3D Extraction Necessities For 5nm And Below

By Ruben Molina - 25 Jan, 2018 - Comments: 0

For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based analysis and path based analysis, on-chip variation modeling, delay calculation, evolving library models, etc. During those years I always understood that parasitic extraction was a crucial element of STA and more impo... » read more

Nodes Vs. Nodelets

By Mark LaPedus - 22 Jan, 2018 - Comments: 0

Foundries are flooding the market with new nodes and different process options at existing nodes, spreading confusion and creating a variety of challenges for chipmakers. There are full-node processes, such as 10nm and 7nm, with 5nm and 3nm in R&D. But there also is an increasing number of half-nodes or "node-lets" being introduced, including 12nm, 11nm, 8nm, 6nm and 4nm. Node-lets ar... » read more

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tag: finFETs

More Nodes, New Problems

New Patterning Options Emerging

Modeling Semiconductor Process Variation

Looking At Test Differently

Tech Talk: 5/3nm Parasitics

Transistor Options Beyond 3nm

New Thermal Issues Emerge

Tech Talk: Applying Machine Learning

3D Extraction Necessities For 5nm And Below

Nodes Vs. Nodelets

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