Experts At The Table: Process Technology Challenges


By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future transistor, process and manufacturing challenges with Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Carlos Mazure, chief technical officer at Soitec; Raj Jammy, senior vice president and general manager of the Semiconductor Group at Intermolecular; and Girish Dixit, v... » read more

It’s A Materials World


By Mark LaPedus At a recent event, Intel’s fab materials guru described a nightmarish occurrence that nearly brought the chip giant to its knees. Tim Hendry, director of fab materials and vice president of the Technology and Manufacturing Group at Intel, said the company obtained a critical material from an undisclosed supplier. “This large sub-supplier, a very large chemical company, m... » read more

The Week In Review: Aug. 12


By Mark LaPedus Is the sky falling on semi capital spending? “We have seen several 2014 industry demand estimates in the 20%+ range, based on the ramps of FinFET and 3D NAND,” said Weston Twigg, an analyst with Pacific Crest Securities. “We expect Samsung to ramp spending in Q4, but we believe foundry and logic spending will remain soft for several quarters. As a result, we are developin... » read more

Power Shifts In Digital Chip Space


By Bhanu Kapoor The power issue has been quite disrupting in the digital semiconductor space. The processor architecture shifted to parallel processing with the “power wall” stopping the frequency scaling that the industry had conveniently used in the last few decades. The power issue also is causing semiconductor process technology to change in ways other than simply scaling from one ... » read more

Materials, Software And Techniques


The future of advanced semiconductor technology is about to split evenly into three different areas. On the leading edge of manufacturing, Applied Materials CEO Mike Splinter called it correctly—it’s all about materials. Just shrinking features isn’t buying much anymore. In fact, at advanced nodes, with extra margin built into designs, it frequently doesn’t buy anything except extra ... » read more

Experts At The Table: Who Pays For Low Power?


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the cost of low power with Fadi Gebara, research staff member for IBM’s Austin Research Lab; David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Aveek Sarkar, vice president of product engineering and support at Apache Design; and Tim Whitfield, director ... » read more

Dealing With New Bottlenecks


By Ed Sperling While the number of options for improving efficiency and performance in designs continues to increase, the number of challenges in getting chips at advanced process nodes out the door is increasing, too. Thinner wires, routing congestion, more power domains, IP integration and lithography issues are conspiring to make design much more difficult than in the past. So why aren�... » read more

New Approaches To Better Performance And Lower Power


By Ed Sperling Until 90nm, every feature shrink and rev of Moore’s Law included a side benefit of better power and performance. After that, improvements involved everything from different back-end processes to copper interconnects and transistor structures. But from 20nm onward, the future will rest with a combination of new materials, new architectures and new packaging approaches—and som... » read more

Intel Vs. Everyone Else


A report from ABI Research is starting to gain some attention. For cynics, the question of why now seems perfectly reasonable, considering the report was released early last month and promptly fell well under the semiconductor industry’s radar. But cynicism aside, it’s still interesting to compare specs for chips using ARM’s Cortex-A15, A9 and Qualcomm’s ARM-based Krait. The bottom ... » read more

Let’s All Meet At The Via Bar!


By Jean-Marie Brunet At 28 nm and below, a variety of new design requirements are forcing us to adjust the traditional layout and verification process of digital designs. The use of vias, in particular, has been significantly impacted. New via types have been introduced, and the addition of double patterning, FinFETS, and other new design techniques has not only generated a considerable increa... » read more

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