tag: finFETs

Tech Talk: 16nm-14nm Effects And Challenges
By Ed Sperling - 06 Nov, 2013 - Comments: 0

Arvind Shanmugavel from Apache Design talks with Semiconductor Engineering about electromigration, electrostatic discharge and thermal effects caused by increasing power density in finFETs.   [youtube vid=GOra5uYyIr8] » read more

Uncertainty, But Not Over Power
By Ed Sperling - 25 Oct, 2013 - Comments: 0

The semiconductor industry has reached a crossroads. Lithography has stalled out, NRE is rising, and chipmakers are torn between choices of when and whether to jump to the next process node—and even more daunting, the next one after that—or whether to take half steps with fan outs, 2.5D, or fully depleted SOI. While chips do continue to tape out, the number of critical choices that need... » read more

Applied-TEL Watch
By Mark LaPedus - 17 Oct, 2013 - Comments: 0

By Mark LaPedus So far this year, the biggest story in the fab tool industry is fairly obvious—Applied Materials recently signed a definitive agreement to acquire rival Tokyo Electron Ltd. (TEL) for about $9.3 billion. The blockbuster announcement will likely be the top story of 2013. Of course, the integration of Applied and TEL will be a challenge. In any case, the Applied-TEL deal is i... » read more

EDA Shows Continued Growth
By Ed Sperling - 16 Oct, 2013 - Comments: 0

EDA and IP revenue jumped 3.8% in Q2 to $1.65 billion, up from $1.59 billion in the same period in 2013, spurred by the need for new tools to design, create and verify SoCs using 16/14nm finFETs. Sequentially, the numbers reported by the EDA Consortium were down slightly from Q1, but the four-quarter moving average—considered a more reliable number because tools sales are long-term investm... » read more

Critical Choices
By Ed Sperling - 10 Oct, 2013 - Comments: 0

There’s been a lot of talk about what’s good enough. Is 10 hours of battery life enough? If the tradeoff is between a smaller battery and extra hour of battery life, which is more important? Those kinds of discussions are at the heart of consumer electronics. Ultra-thin smart phones are more attractive than fat ones, and they’re easier to put in your pocket. But a new kind of discussio... » read more

The Brave New World Of FinFETs
By Ed Sperling - 10 Oct, 2013 - Comments: 0

SoCs using 16nm and 14nm finFETs are expected to begin rolling out next year using a 20nm back-end-of-line process. While the initial performance and power numbers are looking very promising, the challenges of designing and building these complex chips are daunting—and there are more problems on the way. First, the good news. Initial results from foundries show a 150% improvement in perfor... » read more

Reliability Challenges In 16nm FinFET Design
By Arvind Vel - 10 Oct, 2013 - Comments: 1

As the IC industry rapidly adopts the 16nm technology node, IC designers are faced with a new wave of reliability challenges. The 16nm node has introduced several changes in the way that the devices are fabricated and how the metal stack-up is built. On one hand designers gain speed, leakage and density improvements. On the other, reliability engineers need to address the narrowing electromigra... » read more

Manufacturing Bits: Oct. 1
By Mark LaPedus - 01 Oct, 2013 - Comments: 0

Nanoimprint Foundry Singapore’s A*STAR’s Institute of Materials Research and Engineering (IMRE) and its partners have launched a new R&D foundry using nanoimprint lithography. The so-called Nanoimprint Foundry is a collaboration between several entities, such as IMRE, Toshiba Machines, EV Group, NTT, NIL Technology, Kyodo International, Micro Resist Technology, Nanoveu and Solves In... » read more

Viable Choices Ahead
By Ed Sperling - 27 Sep, 2013 - Comments: 0

Two years ago—basically one process node back, wherever companies were on the Moore’s Law road map—there was confusion about what lies ahead and what is the best way to proceed. During that time, three very viable options have been proven to work. Some already are in silicon, while others are coming very soon. The first is the finFET. At the very leading edge of the road map, finFET... » read more

The Week In Review: Sept. 20
By Ed Sperling - 20 Sep, 2013 - Comments: 0

By Ed Sperling It’s reference flow update time as TSMC prepares to roll out both finFETs and stacked die capabilities, and advanced capabilities at 20nm. The foundry updated its reference flows to include tools and IP from all of the Big Three EDA companies. It added Mentor Graphics’ place and route and DFM tools in its 16nm finFET reference flow, and added a slew of Mentor tools, inclu... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy