tag: finFETs

Future Foundry Issues
By Ed Sperling - 13 Jul, 2012 - Comments: 0

Semiconductor Manufacturing & Design talks with Luigi Capodieci, fellow at GlobalFoundries, about EUV, the challenges at 20nm and beyond, and the future of the foundry model. [youtube vid=YXov4y0kpfU] » read more

Dealing With Variability
By Barry Pangrle - 12 Jul, 2012 - Comments: 0

By Barry Pangrle Process, voltage and temperature, a.k.a. PVT, are well known to designers who are working to complete “signoff” for their designs. In order for a design to be production-ready, it’s necessary to ensure that the design is going to yield parts at a sufficiently high percentage for profitability and that it will still operate within the expected variation of the process and... » read more

All Indicators Point North
By Ed Sperling - 28 Jun, 2012 - Comments: 0

Designing and producing chips has always been difficult, but the number of things that conspire to make it harder at 20nm is the longest in the history of the semiconductor industry. The list will grow longer still at 14nm and beyond, not to mention so expensive that one mistake will kill a company. While system engineers and architects look at the challenges on the front end, the problems ... » read more

Experts At The Table: Multipatterning
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Ele... » read more

Fabless-Foundry Model Under Stress
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Mark LaPedus The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond. Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography. ... » read more

FinFET Vs. Tri-Gate
By Barry Pangrle - 05 Apr, 2012 - Comments: 0

By Barry Pangrle A large portion of the Common Platform Technology Forum, recently held in Santa Clara, was dedicated to presentations about 14nm process technologies and FinFETS. If you missed the event and are interested, many of the presentations are available from a link off of the Common Platform home page. Dick James wrote a nice article about GlobalFoundries’ claim that its FinFETS ar... » read more

Crunch Time
By Ed Sperling - 05 Apr, 2012 - Comments: 0

Never have so many things conspired to make design so difficult—at least not at the same time. At the center of this cornucopia of challenges is power, because more functions and more things now have to fit into a power budget that remains fixed. While some components in a complex SoC may run at lower voltages, you can be assured that others will run hotter and at higher voltages—at leas... » read more

Thinking Differently About Power
By Ed Sperling - 12 Jan, 2012 - Comments: 0

By Ed Sperling Battery life and lower electricity bills are now marketing tools for makers of SoCs, the mobile devices they go into, and servers that power data centers. A smart phone battery that lasts through the day without a charge, even when the user is playing high-action games, is a lot more attractive than one lasting only a few hours. And a data center electricity bill that shows a sh... » read more

Off The Planar
By Ed Sperling - 15 Dec, 2011 - Comments: 0

By Pallab Chatterjee 3D devices, FinFETs and new memory technologies are not just a future direction anymore. They’re real. That became evident at this year’s IEDM conference, where the focus of a number of sessions was on modeling, failure and reliability models, as well as lower power supply operations for these devices. Because FinFETs are not standard 2D MOS devices, their use i... » read more

Five Important Changes That Will Affect Power
By Ed Sperling - 03 Nov, 2011 - Comments: 0

By Ed Sperling So far most of the energy savings in SoCs have been achieved using two main approaches—turning off most of the chip most of the time, and changing the materials used to insulate against current leakage. Over the next few years, changes to designs will be more radical, encompass more pieces of a bigger system, and they will be orders of magnitude more effective. From a marke... » read more

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