tag: floorplanning

Using Diffusion Models to Generate Chip Placements (UC Berkeley)
By Technical Paper Link - 27 Jul, 2024 - Comments: 0

A technical paper titled “Chip Placement with Diffusion” was published by researchers at UC Berkeley. Abstract: "Macro placement is a vital step in digital circuit design that defines the physical location of large collections of components, known as macros, on a 2-dimensional chip. The physical layout obtained during placement determines key performance metrics of the chip, such as power... » read more

IC Compiler II: Finding The Best Floorplan, Fast
By Synopsys - 17 Apr, 2024 - Comments: 0

As designers strive to pack more and more functionality into todays’ SoC’s, design size (in terms of the number of transistors packed into a chip) is growing almost exponentially. This growth brings with it an unbounded increase in not just the technical complexity of performing the physical layout of the design due to capacity challenges, but also requires designers to make choices that ca... » read more

Faster And Better Floorplanning With ML-Based Macro Placement
By Synopsys - 03 Apr, 2024 - Comments: 0

The chips contained in today’s consumer and commercial electronic products are staggering in size and complexity. The largest devices include central processing units (CPUs), graphics processing units (GPUs), and system-on-chip (SoC) devices that integrate many functions on a single die. Additionally, chips are expanding beyond their traditional borders with multi-die approaches such as 2.5DI... » read more

AI-Driven Macro Placement Boosts PPA
By Janet Attar - 11 Jan, 2024 - Comments: 0

In the era of EDA 4.0, artificial intelligence (AI) and machine learning (ML) are transforming what electronic design automation tools are capable of. For many of the challenges of physical IC design, AI can provide significant benefits to both the turnaround time and the quality of the design, as measured by performance, power, and area (PPA) metrics. One implementation step due for improve... » read more

A Path To Increase Cell Utilization Rate And Decrease Routing Congestion In Chip Design Floorplanning
By Jim Schultz - 30 Nov, 2023 - Comments: 0

What do chip floorplanning and city planning have in common? As it turns out, quite a lot. This was the premise for an award-winning talk given by MediaTek at this year’s Synopsys User Group (SNUG) in Taiwan. Urban city development was used as an example to understand how utilization rate (UR) and congestion relate to chip planning. UR was defined in the example as population density while... » read more

Ensuring Memory Reliability Throughout the Silicon Lifecycle
By Anand Thiruvengadam - 14 Nov, 2022 - Comments: 0

By Anand Thiruvengadam and Guy Cortez Memories are everywhere in modern electronics. Discrete memory chips account for much of the space on printed circuit boards (PCBs). Embedded memories consume much of the floorplan in system-on-chip (SoC) devices. Many multi-die chip configurations, including 2.5D/3DIC devices, are driven by the need for faster memory access. Designing and verifying memo... » read more

A graph placement methodology for fast chip design
By Technical Paper Link - 09 Nov, 2021 - Comments: 0

Abstract "Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research1, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method autom... » read more

NoC Experiences From The Trenches
By Kurt Shuler - 28 Sep, 2021 - Comments: 0

Network-on-chip (NoC) interconnect as an alternative to traditional crossbars is already well-proven, but there are still plenty of design teams on the cusp of a transition or who maybe do not yet see a need for a change. As with a switch to any new technology, the first hurdles are often simply misconceptions. When new users first evaluate any new technology, they often make the mistake of att... » read more

PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning
By Technical Paper Link - 31 Dec, 2020 - Comments: 0

Academic research paper from Dept. of CSE, IIT Guwahatim, India. Abstract: "With the increase in the complexity of chip designs, VLSI physical design has become a time-consuming task, which is an iterative design process. Power planning is that part of the floorplanning in VLSI physical design where power grid networks are designed in order to provide adequate power to all the underlying ... » read more

Can Machine Learning Chips Help Develop Better Tools With Machine Learning?
By Vinay Patwardhan - 18 Jun, 2018 - Comments: 0

As we continue to be bombarded with AI- and machine learning-themed presentations at industry conferences, an ex-colleague told me that he is sick of seeing an outline of the human head with a processor in place of the brain. If you are a chip architect trying to build one of these data-centric architecture chips for machine learning or AI (as opposed to the compute-centric chips, which you pro... » read more

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