tag: FPGAs

New Security Approaches, New Threats
By Ed Sperling - 09 Dec, 2020 - Comments: 0

New and different approaches to security are gaining a foothold as the life expectancy for advanced chips increases, and as emerging technologies such as quantum computing threaten to crack even the most complex encryption schemes. These approaches include everything from homomorphic encryption, where data is processed without being decrypted, to different ways of sending and receiving data ... » read more

Security Tradeoffs In Chips And AI Systems
By Ed Sperling - 03 Nov, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss the cost and effectiveness of security in chip architectures and AI systems with with Vic Kulkarni, vice president and chief strategist at Ansys; Jason Oberg, CTO and co-founder of Tortuga Logic; Pamela Norton, CEO and founder of Borsetta; Ron Perez, fellow and technical lead for security architecture at Intel; and Tim Whitfield, vice president of s... » read more

Intelligent System Design
By Cadence - 02 Sep, 2020 - Comments: 0

Electronics technology is proliferating to new, creative applications and appearing in our everyday lives. To compete, system companies are increasingly designing their own semiconductor chips, and semiconductor companies are delivering software stacks, to enable substantial differentiation of their products. This trend started in mobile devices and is now moving into cloud computing, automotiv... » read more

The Challenge Of Keeping AI Systems Current
By Ed Sperling And Susan Rambo - 19 Aug, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss AI and its move to the edge with Steven Woo, vice president of enterprise solutions technology and distinguished inventor at Rambus; Kris Ardis, executive director at Maxim Integrated; Steve Roddy, vice president of Arm's Products Learning Group; and Vinay Mehta, inference technical marketing manager at Flex Logix. What follows are excerpts of that ... » read more

Power Impact At The Physical Layer Causes Downstream Effects
By Ann Mutschler - 09 Jul, 2020 - Comments: 0

Data movement is rapidly emerging as one of the top design challenges, and it is being complicated by new chip architectures and physical effects caused by increasing density at advanced nodes and in multi-chip systems. Until the introduction of the latest revs of high-bandwidth memory, as well as GDDR6, memory was considered the next big bottleneck. But other compute bottlenecks have been e... » read more

Real Highlights For Virtual DAC 2020
By Sergio Marchese - 25 Jun, 2020 - Comments: 0

My first time at DAC was in 2006 in San Francisco. I was mesmerized by it: so many people, so much cool technology, so much fun with weird giveaways, raffles, happy hours, the Denali party and Disco Inferno at the legendary Fillmore. DAC is the most important, comprehensive conference for anyone developing integrated circuits (ICs) and systems-on-chips (SoCs). With an incredible list of ... » read more

ML Opening New Doors For FPGAs
By Bryon Moyer - 24 Jun, 2020 - Comments: 0

FPGAs have long been used in the early stages of any new digital technology, given their utility for prototyping and rapid evolution. But with machine learning, FPGAs are showing benefits beyond those of more conventional solutions. This opens up a hot new market for FPGAs, which traditionally have been hard to sustain in high-volume production due to pricing, and hard to use for battery-dri... » read more

Fundamental Changes In Economics Of Chip Security
By Ed Sperling - 10 Jun, 2020 - Comments: 0

Protecting chips from cyberattacks is becoming more difficult, more expensive and much more resource-intensive, but it also is becoming increasingly necessary as some of those chips end up in mission-critical servers and in safety-critical applications such as automotive. Security has been on the semiconductor industry's radar for at least the past several years, despite spotty progress and ... » read more

Rethinking Your Approach To Radiation Mitigation
By Mentor, a Siemens Business - 03 Jun, 2020 - Comments: 0

Formal verification and automation provide an effective, high quality, and repeatable process for fault analysis, protection, and verification for FPGA designs used in high radiation environments. This paper describes an automated systematic approach based on formal verification structural and static analysis that identifies design susceptibility to radiation induced faults. To read more, clic... » read more

FPGA Prototyping Complexity Rising
By Ann Mutschler - 28 May, 2020 - Comments: 0

Multi-FPGA prototyping of ASIC and SoC designs allows verification teams to achieve the highest clock rates among emulation techniques, but setting up the design for prototyping is complicated and challenging. This is where machine learning and other new approaches are beginning to help. The underlying problem is that designs are becoming so large and complex that they have to be partitioned... » read more

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