One-On-One: Aaron Thean


Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec. SE: Chipmakers are ramping up the 16nm/14nm logic node, with 10nm and 7nm in R&D. What’s the current timeline for 10nm and 7nm? Thean: 10nm is on its way. We will see r... » read more

Unraveling The Mysteries At IEDM


In some respects, the 2014 IEEE International Electron Devices Meeting (IEDM) was no different than past events. The event, held this week in San Francisco, included the usual and dizzying array of tutorials, sessions, papers and panels. On the leading-edge CMOS front, for example, the topics included [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D IC"] chips, III-V materials, [getkc ... » read more

And the Winner is…


Semiconductor Engineering now has its first full year under its belt, and I have to say it has been an incredible year. Not only did we exceed a million page views in our first year, but we also got started on the Knowledge Center, an endeavor the likes of which has never been attempted in our industry. It is still very young and has a lot of growing up to do, but it is a wonderful start. We wo... » read more

Transistor Options Narrow For 7nm


Chipmakers are currently ramping up silicon-based finFETs at the 16nm/14nm node, with plans to scale the same technology to 10nm. Now, the industry is focusing on the transistor options for 7nm and beyond. At one time, the leading contenders involved several next-generation transistor types. At present, the industry is narrowing down the options and one technology is taking a surprising lea... » read more

Re-Engineering The FinFET


The semiconductor industry is still in the early stages of the [getkc id="185" kc_name="finFET"] era, but the [getkc id="26" kc_name="transistor"] technology already is undergoing a dramatic change. The fins themselves are getting a makeover. In the first-generation finFETs, the fins were relatively short and tapered. In the next wave, the fins are expected to get taller, thinner and more re... » read more

Will 7nm And 5nm Really Happen?


As leading-edge chipmakers continue to ramp up their 28nm and 20nm devices, vendors are also updating their future technology roadmaps. In fact, IC makers are talking about their new shipment schedules for 10nm. And GlobalFoundries, Intel, Samsung and TSMC are narrowing down the options for 7nm, 5nm and beyond. There is a high probability that IC makers can scale to 10nm, but vendors face a ... » read more

Manufacturing Bits: June 10


Self-Assembling Nano Films Applying thin films with uniformity has always been an engineering challenge, but as feature sizes shrink the problem become even more pronounced. But a new approach developed by Lawrence Berkeley National Labs’ Materials Science Division could end up simplifying this process. The new approach used chloroform as an annealing solvent to create self-assembling arr... » read more

Power Moves Up To First Place


Virtually every presentation delivered about semiconductor design or manufacturing these days—and every end product specification that uses advanced technology—incorporates some reference to power and/or energy. It has emerged as the most persistent, most problematic, and certainly the most talked about issue from conception to marketplace adoption. And the conversation only grows louder... » read more

New Challenges For Post-Silicon Channel Materials


In order to bring alternative channel materials into the CMOS mainstream, manufacturers need not just individual transistor devices, but fully manufacturable process flows. Work presented at the recent IEEE Electron Device Meeting (Washington, D.C., Dec. 9-11, 2013) showed that substantial work remains to be done on almost all aspects of such a flow. First and most fundamentally, it is diffi... » read more

The Search For The Next Transistor


In the near term, the leading-edge chip roadmap looks fairly clear. Chips based on today’s finFETs and planar fully depleted silicon-on-insulator (FDSOI) technologies are expected to scale down to the 10nm node. But then, the CMOS roadmap becomes foggy at 7nm and beyond. The industry has been exploring a number of next-generation transistor candidates, but suddenly, a few technologies are ... » read more

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