tag: Ghent University

A Framework For Improving Current Defect Inspection Techniques For Advanced Nodes
By Technical Paper Link - 12 Dec, 2023 - Comments: 0

A technical paper titled “Improved Defect Detection and Classification Method for Advanced IC Nodes by Using Slicing Aided Hyper Inference with Refinement Strategy” was published by researchers at Ghent University, imec, and SCREEN SPE. Abstract: "In semiconductor manufacturing, lithography has often been the manufacturing step defining the smallest possible pattern dimensions. In recent ... » read more

Chip Industry Week In Review
By The SE Staff - 06 Oct, 2023 - Comments: 0

By Jesse Allen, Liz Allan, and Gregory Haley A potential government shutdown beginning in November would be "massively disruptive" for the Commerce Department as it continues to disburse critical funding featured in the CHIPS Act to boost semiconductor research and development in the U.S., according to Secretary Gina Raimondo. Global semiconductor industry sales totaled $44 billion in Aug... » read more

Research Bits: April 4
By Jesse Allen - 04 Apr, 2023 - Comments: 0

Wet-like plasma etching Researchers from Nagoya University and Hitachi developed a new etch method called wet-like plasma etching that combines the selectivity of wet etching with the controllability of dry etching. The researchers say the technique will make it possible to etch complex structures such as metal carbides consisting of titanium (Ti) and aluminum (Al), such as TiC or TiAlC, wh... » read more

Chip Industry’s Technical Paper Roundup: Mar. 28
By Linda Christensen - 28 Mar, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=89 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us p... » read more

Integrating MEMS with Standardized Silicon Photonics Technology
By Technical Paper Link - 23 Mar, 2023 - Comments: 0

A new technical paper titled "Integrated silicon photonic MEMS" was published by researchers at EPFL, University of Sydney, CSEM, KTH Royal Institute of Technology, Ghent University, Imec, and Tyndall National Institute. Abstract Excerpt "Here, we introduce a silicon photonic MEMS platform consisting of high-performance nano-opto-electromechanical devices fully integrated alongside standar... » read more

Chip Industry’s Technical Paper Roundup: Nov. 29
By Linda Christensen - 29 Nov, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=66 /]   Related Reading: Chip Industry’s Technical Paper Roundup: Nov. 21 New papers: lithography modeling; solving Rowhammer; energy-efficient batch normalization HW; 3-to-1 reconfigurable analog signal modulation circuit; lateral double magnetic tunnel junction; reduce branch mispredic... » read more

Wafer-Scale Variability In Photonic Devices & Effects On Circuits
By Technical Paper Link - 25 Nov, 2022 - Comments: 0

A technical paper titled "Capturing the Effects of Spatial Process Variations in Silicon Photonic Circuits" was published by researchers at Photonics Research Group, Ghent University−IMEC. "We present in this paper a method to extract a granular map of the line width and thickness variation on a silicon photonics wafer. We propose a hierarchical model to separate the layout-dependent and l... » read more

High-NA EUV May Be Closer Than It Appears
By Katherine Derbyshire - 16 Jun, 2022 - Comments: 1

High-NA EUV is on track to enable scaling down to the Angstrom level, setting the stage for chips with even higher transistor counts and a whole new wave of tools, materials, and system architectures. At the recent SPIE Advanced Lithography conference, Mark Phillips, director of lithography hardware and solutions at Intel, reiterated the company’s intention to deploy the technology in high... » read more

Photomask Challenges At 3nm And Beyond
By Mark LaPedus - 25 Jan, 2022 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss optical and EUV photomasks issues, as well as the challenges facing the mask business, with Naoya Hayashi, research fellow at DNP; Peter Buck, director of MPC & mask defect management at Siemens Digital Industries Software; Bryan Kasprowicz, senior director of technical strategy at Hoya; and Aki Fujimura, CEO of D2S. What f... » read more

Why Mask Blanks Are Critical
By Mark LaPedus - 21 Oct, 2021 - Comments: 1

Geoff Akiki, president of Hoya LSI at the Hoya Group, sat down with Semiconductor Engineering to talk about optical and extreme ultraviolet (EUV) lithography as well as mask blanks. What follows are excerpts of that discussion. SE: Mask blanks are components that serve as the base or the substrate for a photomask. Why are they critical? Akiki: If you look at Hoya, we've been positioned as... » read more

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