tag: GlobalFoundries

Experts At The Table: Issues In Metrology And Inspection
By Mark LaPedus - 18 Apr, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future metrology and inspection challenges with John Allgair, senior member of the technical staff at GlobalFoundries; Kevin Heidrich, vice president of marketing and business development at Nanometrics; Robert Newcomb, executive vice president at Qcept Technologies; and Shrinivas Shetty, vice president of marketing f... » read more

MEMS Explosion
By Rakesh Kumar - 18 Apr, 2013 - Comments: 0

By Rakesh Kumar The MEMS market is set to explode. By 2017 the market is expected to be worth $12.2 billion, a 50% increase from 2011, according to IHS iSuppli. Driving this growth will be the continued usage of MEMs devices for consumer applications, such as smartphones, tablets, gaming consoles and cameras. Additionally, new products such as silicon timing devices, tunable capacitors for ant... » read more

GF’S Two Flavors Of FD-SOI
By Various Writers - 17 Apr, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ Hearing the news that GlobalFoundries would be offering two flavors of FD-SOI, ASN asked the company to explain the strategy further. Here are the responses provided by Subi Kengeri, Vice President of Advanced Technology Architecture.   [caption id="" align="alignleft" width="110"] Subi Kengeri, VP Advanced T... » read more

Uncertainty Ahead
By Ed Sperling - 11 Apr, 2013 - Comments: 0

If finFETs work as planned, it’s likely they will show up in every complex SoC for decades to come. Adding another dimension to transistors has enormous potential at advanced nodes, and maybe even at older nodes. 3D transistors also could be part of stacked die, and they can be combined with fully depleted SOI—two other options for reducing power. Moreover, it’s likely that whatever G... » read more

Wanted: New Metrology Funding Models
By Mark LaPedus - 21 Mar, 2013 - Comments: 0

By Mark LaPedus The shift toward the 20nm node and beyond will require new and major breakthroughs in chip manufacturing. Most of the attention centers around lithography, gate stacks, interconnects, strain engineering and design-for-manufacturing (DFM). Lost in the conversation are two other critical but overlooked pieces in the manufacturing puzzle—wafer inspection and metrology. ... » read more

Reaching For The Reset Button In Lithography
By Mark LaPedus - 21 Mar, 2013 - Comments: 0

By Mark LaPedus Amid ongoing delays and setbacks, extreme ultraviolet (EUV) lithography and multi-beam e-beam have both missed the 10nm logic node. So for the present, chipmakers must take the brute force route at 10nm by using 193nm immersion with multiple patterning. Now, it’s time to hit the reset button. For the 7nm node, chipmakers currently are lining up the lithographic competition... » read more

Directed Self-Assembly Grows Up
By Mark LaPedus - 21 Mar, 2013 - Comments: 1

By Mark LaPedus At last year’s SPIE Advanced Lithography conference, Christopher Bencher, a member of the technical staff at Applied Materials, said the buzz surrounding directed self-assembly (DSA) technology resembled the fervor generated at the famous Woodstock rock concert in 1969. This was clearly evident from the tumultuous and free-flowing movement that threatened the status quo o... » read more

Swimming In Data
By Ed Sperling - 21 Mar, 2013 - Comments: 0

By Ed Sperling So many warnings about data overload have been issued over the past decade that people generally have stopped paying attention to them. The numbers are so astronomical that increases tend to lose meaning. Nowhere is this more evident than in the semiconductor metrology world, where files are measured in gigabytes. And at each new process node, as the number of transistors a... » read more

What’s In A Name?
By Subi Kengeri - 20 Mar, 2013 - Comments: 0

By Subi Kengeri Consumers continue to demand smaller, faster and more energy-efficient electronic devices, driving the semiconductor industry to accelerate development of commercially viable chips on more advanced nodes. However, these new nodes don’t just appear by magic. It takes a great deal of careful planning to develop and deliver a process technology platform that offers competitivene... » read more

Version Control
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling & Ann Steffora Mutschler One of the biggest impediments to progress in semiconductor design is progress itself—version after version of specifications, formats and increasingly IP. In fact, there are so many different versions, some of which conflict directly with each other, that it may take months or even years before some customers adopt new products. Much has ... » read more

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