tag: GlobalFoundries

Raising The Stakes For IP
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling As the amount of IP in an SoC increases, so do the number of players who want to strengthen their position in this market. The big acquisitions that began several years ago over time have proved to be just opening salvos—something that was impossible to predict when this shift began. Synopsys’ purchase of Virage Logic and Cadence’s purchase of Denali, both of which occu... » read more

Uncommon Goals
By Atrenta - 14 Feb, 2013 - Comments: 0

I had the opportunity to attend the Common Platform event recently. This is a technology and business showcase sponsored by Global Foundries, IBM and Samsung with major support from ARM, Cadence, Synopsys and Mentor. Wow, that’s some serious sponsorship. The event was well run and provided a good balance of technology details and business outlook. The wine at the evening reception was decent ... » read more

Math Questions
By Ed Sperling - 08 Feb, 2013 - Comments: 0

The race is on. GlobalFoundries, TSMC, Samsung, IBM and Intel are all neck deep in research, test chips, variability, lithography and three-dimensional transistor designs. For the first time, though, the goal very publicly has shifted from performance and area to energy efficiency. Being able to double battery life with existing performance over the next couple nodes could mean smart phones ... » read more

Stacked Die From A Networking Angle
By Mark LaPedus - 24 Jan, 2013 - Comments: 1

By Mark LaPedus The first wave of 2.5D chips using silicon interposers are trickling out in the marketplace.FPGA vendor Xilinx was the first chipmaker to ship a 2.5D device, and Altera, Cisco, Huawei and IBM recently have talked about their respective 2.5D chip developments. Generally, Altera and Xilinx have taken a somewhat identical and straightforward approach. The two companies are sepa... » read more

ST-Ericsson 28nm FD-SOI/ARM Chip Hits 2.8GHz at CES
By Various Writers - 22 Jan, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ What a great start to 2013: at CES in Las Vegas, ST-Ericsson announced the NovaThor™ L8580 ModAp, “the world’s fastest and lowest-power integrated LTE smartphone platform.” This is the one that’s on STMicroelectronics’ 28nm FD-SOI, with sampling set for Q1 2013. And it’s a game changer – for users, fo... » read more

Too Many Rules
By Ed Sperling - 13 Dec, 2012 - Comments: 0

By Ed Sperling The number of restrictive design rules that have to be dealt with by routers at 28nm and beyond has increased by several orders of magnitude compared with several generations ago, creating havoc in the automated tools world and slowing down the entire design process. At a time when market windows are shrinking, complexity is making it harder to meet even the old schedules. Th... » read more

What’s Before Stacked Die?
By Mark LaPedus - 13 Dec, 2012 - Comments: 0

By Mark LaPedus Advanced 2.5D/3D chip stacking has a number of challenges and is still a few years away from mass production. In fact, mass production may not occur until 2015 or 2016. But OEMs can ill afford to sit still and wait for 2.5D/3D technology to mature. So, until 2.5D/3D is ready for prime time, chipmakers and IC-packaging houses are under pressure to innovate and extend current ... » read more

Foundry Landscape Changes In 3D
By Mark LaPedus - 13 Dec, 2012 - Comments: 0

By Mark LaPedus Over the last year, leading-edge silicon foundries announced their new and respective strategies in the emerging 2.5D/3D chip arena. The ink is barely dry and now the foundry landscape is changing. One new vendor, Tezzaron Semiconductor, is entering the market. The 3D DRAM supplier plans to provide select 2.5D/3D foundry services within its recently acquired fab in Austin, T... » read more

DFM Challenges Abound Below 20nm
By Ed Sperling - 13 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler As semiconductor design teams struggle to wring the last few percentage of die shrink from a technology node, much of the ability to do that rests on the EDA tools. From place and route through DFM checks—essentially, everything that happens before the design is sent to the fab or foundry—it all must be tightly integrated with the manufacturing process so it co... » read more

Mix-And-Match Power Options
By Ed Sperling - 06 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler Choices abound today when it comes to considering a node shrink. Fully depleted silicon on insulator (FD-SOI) and finFET technologies along with other advanced transistor options are being evaluated, both together and independently of the other. It is possible to implement finFET on bulk 28nm CMOS or finFET on an FD-SOI process, for example. It is also possible to imp... » read more

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