What’s Before Stacked Die?

IC houses are working on packaging to extend 2D while the market gets ready for the big shift; packaging options emerge, including alternatives to TSVs.


By Mark LaPedus
Advanced 2.5D/3D chip stacking has a number of challenges and is still a few years away from mass production.

In fact, mass production may not occur until 2015 or 2016. But OEMs can ill afford to sit still and wait for 2.5D/3D technology to mature. So, until 2.5D/3D is ready for prime time, chipmakers and IC-packaging houses are under pressure to innovate and extend current 2D-based technology.

Needless to say, OEMs demand smaller and lower power chips housed in thinner packages. “The silicon is getting more dense. There are also more I/Os on the chip. Packaging is becoming the burden,” said Raj Pendse, vice president and chief marketing officer at STATS ChipPAC.

In fact, IC-packaging houses currently are developing a dizzying array of new package types that promise to extend 2D technology. For example, the subcontractors are working on new packages that could evolve or replace the mainstream mobile technology: package-on-package (PoP). The next-generation PoP candidates include bond via array, embedded PoP, fan-in, fan-out, flip-chip PoP, and even multi-chip modules (MCMs).

“The mobile phone platform is essentially becoming one big package,” said Rich Rice, senior vice president of sales for North America at Advanced Semiconductor Engineering (ASE). “Your cell phone motherboard, in a sense, is becoming a multi-chip module.”

Surprise package
For decades, IC packaging mainly involved low-tech, labor-intensive work with a plethora of simple package types, such as DIPs, PGAs, PLCCs and QFPs. “Packaging used to be an afterthought,” said STATS ChipPAC’s Pendse. “Silicon was once the solution. The main goal of packaging was to encase the silicon so it wouldn’t fall apart.”

In the 1980s and 1990s, the world changed with the emergence of new consumer electronic items and the PC. IC packaging still remained in the shadows despite various innovations like BGA, CSP and flip-chip. More recently, there has been a sea of change in the industry. Chip complexity is increasing, but the geometries are shrinking. The boom in mobile is driving the need for new and thinner packages.

For example, there is a pressing need for a thinner PoP. Introduced several years ago for the mobile space, PoP is used for devices like ASICs, baseband chips and application processors. PoP combines separate logic and memory packages, which are stacked on top of each other. The bottom package is logic and the top is memory. The maximum height of the PoP packages is typically 1.4mm to 1.6mm, but the eventual goal is to drive the dimensions down to 1mm and below.

There are other design considerations. At the 65nm node, a processor had some 400 I/Os and consumed 400mW of power on a die size of 64mm-square, according to a recent presentation from DfR Solutions. But at 28nm, a processor has some 800 I/Os and consumes 1.2 Watts of power on a die size of 50mm-square, according to the firm.

Still, in next-generation mobile designs, the industry may need to shrink the PoP to 0.4mm. One way to boost PoP densities is a technology called fine-pitch copper pillar flip-chip packaging. “Copper pillar can help enable a smaller form factor for the bottom package,” said E. Jan Vardaman, president of TechSearch International, a research firm.

Copper pillar is not a packaging type per se, but it is a manufacturing technique to enable next-generation CSPs, PoPs and even 2.5D/3D chips. The technology moved into the limelight in 2010, when Texas Instruments and Amkor jointly rolled out copper pillar capabilities.

At the time, TI said that traditional wire-bonding technology would hit the wall at the 40nm node, thereby requiring copper-pillar flip-chip. In flip-chip, a device is mounted on a substrate face down. Traditional solder-based flip-chip is limited to 150um pitches. In copper-pillar, however, the pitches can be extended down to 50um in-line and 40um/80um staggered, according to Amkor.

In PoP, the top and bottom chips could be individually packaged using wire bonders. In another configuration, the top package could be wire-bonded, while the bottom package could implement copper-pillar flip-chip. Using copper pillar for the bottom package, PoP may be more expensive, but it enables higher I/O densities and increased thermal conductivity.

Flip-chip took several years to gain traction, but it is widely used for processors and graphics chips today. The lowly wire-bonder continues to have legs, as some 80% of the world’s chips are still assembled using wire-bonding techniques, according to Vardaman. “Wire-bonding will be around for a long, long time,” she said during a recent presentation at an event sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC).

For years, the lead wires in wire bonding were based primarily on gold. Gold prices have skyrocketed in recent years, prompting many chipmakers to move to cheaper copper wiring. “Three years ago, the industry said wire bonding would not extend past 40nm,” said Y.S Kim, vice president of engineering at Signetics, an IC packaging house. “We are now qualifying copper wire bonding at 32nm.”

Signetics is also doubling its capacity for flip-chip package assembly within its factory in Paju, South Korea. The company offers standard bumping and copper-pillar flip-chip. The technology is being driven by finer-pitch packages in HDTVs, SSDs and smartphones.

Time for another PoP?
Besides flip-chip PoP, there are other next-generation PoP candidates, such as embedded wafer level ball grid array (eWLB). In typical wafer-level packages, the process steps are performed on the wafer and the interconnects are fit on the chip in a fan-in design. In eWLB, the interconnects are positioned in an arbitrary distance in a fan-out design. Unlike fan-in, eWLB’s package size and I/O count are not limited by the die size.

Infineon, STATS ChipPAC and others are pushing eWLB. With fan out, STATS ChipPAC can reduce the bottom PoP package in height to less than 0.5mm. Using fan out, the total height for a five-die package is less than 1mm. STATS ChipPAC is shipping multi-die versions of fan out packages in a 300mm manufacturing process.

The next step is to bring eWLB into the 2.5D/3D era. With the technology, STATS ChipPAC can embed multiple active and passive components in the same wafer-level package with a vertical 3D interconnection that can be achieved without the use of a TSV. “It is positioned for 2.5D integration. It’s an alternative (to 3D TSV),” said STATS ChipPAC’s Pendse.

Rival ASE is moving in a slightly different direction. Like STATS ChipPAC, ASE was an early licensee of eWLB from Infineon. Fan out requires a different tool and materials infrastructure. “The investment level is much higher,” said ASE’s Rice. “We are manufacturing it on 200mm. For 300mm, we chose not to do it.”

ASE and others are pursuing so-called embedded PoP. In embedded PoP, the die is embedded in the substrate in the bottom of the package. “You may embed a passive or active component in the substrate itself,” Rice said.

The idea is to embed components, such as the capacitors or power management devices, close to the I/O of the processor die. Embedded PoP could reduce the space and power consumption in mobile devices. It also has many of the challenges associated with MCMs. Embedded PoP may require bare die, which is difficult to handle and test. “It disrupts the supply chain on how substrates are made,” he said.

Embedding die into laminated substrates has been in development for years. For example, TI recently rolled out MicroSiP, a miniaturized system-in-package (SiP). MicroSiP is not a PoP package. Instead, it integrates ICs with passive components in a BGA format. The passives are arranged on the top, while BGA balls are arrayed on the bottom.

Then, a separate package, dubbed PicoStar, is embedded in the laminate substrate. All told, the combined MicroSiP/PicoStar package integrates a DC-to-DC converter with inductors and capacitors to provide a stand-alone power supply, said David Heacock, senior vice president of Silicon Valley Analog at TI.

In another PoP effort, Invensas, a subsidiary of Tessera, recently unveiled bond via array (BVA) technology. BVA PoP is a packaging alternative to Wide I/O. It has demonstrated scalability to a 0.2mm pitch and up to 1,400 I/Os. “BVA significantly pushes out the need for 3D TSV. At the same time, it renders solder via obsolete as it is able to cost-effectively scale to ultra-high I/O,” said Simon McElrea, president of Invensas.

Clearly, there are new PoP solutions waiting in the wings. OEMs will need to take a hard look at the new technologies and for good reason: 2.5D/3D technology is still not ready for prime time. “For 2.5D, 2014 will be a very interesting year. By the end of 2013, the capability will be in place. 3D mainly depends on memory standards and memory adoption,” said Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries.

Steve Pateras, product marketing director at Mentor Graphics, added: “From a tapeout point of view, 2.5D is happening this year. We have customers taping out 2.5D. For 3D, we’re seeing design activity for memory on logic. Next year we’ll see some tapeouts. There is no real activity in logic on logic yet.”

In any case, the role of packaging is changing. Packaging is no longer an afterthought. It is becoming an important part of the IC design and manufacturing process. “Today, it is an important part of the solution,” STATS ChipPAC’s Pendse said.

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