A Safety Island For Safe Use of HPC Devices For Safety-Critical Systems with RISC-V


A technical paper titled “Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains” was published by researchers at Barcelona Supercomputing Center and Intel. Abstract: "HPC (High Performance Computing) devices increasingly become the only alternative to deliver the performance needed in safety-critical autonomous systems (e.g., autonomous cars, unmanned planes) du... » read more

Placement And CTS Techniques For High-Performance Computing Designs


This paper discusses the challenges of designing high-performance computing (HPC) integrated circuits (ICs) to achieve maximum performance. The design process for HPC ICs has become more complex with each new process technology, requiring new architectures and transistors. We highlight how the Siemens Aprisa digital implementation solution can solve placement and clock tree challenges in HPC de... » read more

Improved Arm Server Price-Performance For HPC


The availability of Amazon EC2 Hpc7g instances with the AWS Graviton3E and Elastic Fabric Adapter (EFA) is opening new opportunities in key areas: Manufacturing Aerospace Automotive engineering Weather prediction The new AWS EC2 instance types have AWS Graviton3E’s 64 Arm Neoverse V1 cores and 8 channels of DDR5 memory. This is alongside the AWS Nitro v5 card with EFA deliver... » read more

Redox-Based Ionic Devices For High-Performance Neuromorphic Computing


A technical paper titled "A Redox-Based Ion-Gating Reservoir, Utilizing Double Reservoir States in Drain and Gate Nonlinear Responses" was published by researchers at National Institute for Materials Science (NIMS) and Tokyo University of Science. Abstract: "Herein, physical reservoir computing with a redox-based ion-gating reservoir (redox-IGR) comprising LixWO3 thin film and lithium-ion co... » read more

Tools for Co-Designing HPC Systems Using RISC-V As A Demonstrator


A technical paper titled “Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study” was published by researchers at Barcelona Supercomputing Center and FORTH. Abstract: "Prototyping HPC systems with low-to-mid technology readiness level (TRL) systems is critical for providing feedback to hardware designers, the system software team (e.g., co... » read more

Top500: Frontier Is Still On Top


The latest versions of the Top500 and Green500 lists were just released on May 22, 2023. The last time that I wrote about the Green500, a Chinese machine, NRCPC’s Sunway TaihuLight, was sitting at the top of the Top500 list. It’s been a while since I last wrote about these lists and it’s interesting to look back at the leap in performance and energy efficiency over the past 7 years. ... » read more

Conquer Placement And Clock Tree Challenges In HPC Designs


High-performance computing (HPC) applications require IC designs with maximum performance. However, as process technology advances, achieving high performance has become increasingly challenging. Designers need digital implementation tools and methodologies that can solve the thorny issues in HPC designs, including placement and clock tree challenges. Placement and clock tree synthesis are c... » read more

Placement And CTS Techniques For High-Performance Computing Designs


This paper discusses the challenges of designing high-performance computing (HPC) integrated circuits (ICs) to achieve maximum performance. The design process for HPC ICs has become more complex with each new process technology, requiring new architectures and transistors. We highlight how the Siemens Aprisa digital implementation solution can solve placement and clock tree challenges in HPC de... » read more

RISC-V Vectorization And Potential for HPC


A new technical paper titled "Test-driving RISC-V Vector hardware for HPC" was published by researchers at University of Edinburgh. Abstract: "Whilst the RISC-V Vector extension (RVV) has been ratified, at the time of writing both hardware implementations and open source software support are still limited for vectorisation on RISC-V. This is important because vectorisation is crucial to obt... » read more

A RISC-V On-Chip Parallel Power Controller for HPC (ETH Zurich, U. of Bologna)


A new technical paper titled "ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation" was published (preprint) by researchers at ETH Zurich and University of Bologna. Abstract (partial) "High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex an... » read more

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