tag: IEEE

Is There a Practical Test For Rowhammer Vulnerability?
By Bryon Moyer - 08 Jun, 2021 - Comments: 3

Rowhammer is proving to be a difficult DRAM issue to fix. While efforts continue to mitigate or eliminate the effect, no solid solution has yet made it to volume production. In addition, more aggressive process nodes are expected to exacerbate the problem. In the absence of a fix, then, testing may be one way to give DRAM manufacturers and users some way to segregate devices that are more su... » read more

Where Imperfections Lead To Opportunity
By Evelyn Hu - 07 Jun, 2021 - Comments: 0

By Evelyn Hu It is natural to hold a bias that assumes that the highest-quality devices are those formed from the most perfect materials (crystalline, well-ordered, stoichiometric). Therefore, it is ironic, and perhaps counterintuitive, that particular kinds of defects, such as vacancies (missing atoms) in semiconductor materials, can form the building blocks of a new quantum information tec... » read more

The Increasingly Uneven Race To 3nm/2nm
By Mark LaPedus and Ed Sperling - 24 May, 2021 - Comments: 2

Several chipmakers and fabless design houses are racing against each other to develop processes and chips at the next logic nodes in 3nm and 2nm, but putting these technologies into mass production is proving both expensive and difficult. It's also beginning to raise questions about just how quickly those new nodes will be needed and why. Migrating to the next nodes does boost performance an... » read more

Chasing Test Escapes In IC Manufacturing
By Anne Meixner - 11 May, 2021 - Comments: 0

The number of bad chips that slip through testing and end up in the field can be significantly reduced before those devices ever leave the fab, but the cost of developing the necessary tests and analyzing the data has sharply limited adoption. Determining an acceptable test escape metric for an IC is essential to improving the yield-to-quality ratio in chip manufacturing, but what exactly is... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 07 May, 2021 - Comments: 0

Pervasive computing — IoT, edge, cloud, data center, and back Foxconn (also known as Hon Hai Technology Group) is forming a joint venture (JV) with Yageo Group, a component production and process management company for EVs and other high-end electronics, to focus on the development of semiconductors under $2 USD, which they call “small ICs.” Through the JV, a new company called XSemi wil... » read more

Part Average Tests For Auto ICs Not Good Enough
By Anne Meixner - 24 Feb, 2021 - Comments: 0

Part Average Testing (PAT) has long been used in automotive. For some semiconductor technologies it remains viable, while for others it is no longer good enough. Automakers are bracing for chips developed at advanced process nodes with much trepidation. Tight control of their supply chains and a reliance upon mature electronic processes so far have enabled them to increase electronic compone... » read more

Manufacturing Bits: Feb. 2
By Mark LaPedus - 02 Feb, 2021 - Comments: 0

Capacitor-less DRAM At the recent 2020 International Electron Devices Meeting (IEDM), Imec presented a paper on a novel capacitor-less DRAM cell architecture. DRAM is used for main memory in systems, and today’s most advanced devices are based on roughly 18nm to 15nm processes. The physical limit for DRAM is somewhere around 10nm. DRAM itself is based on a one-transistor, one-capacito... » read more

Manufacturing Bits: Dec. 29
By Mark LaPedus - 29 Dec, 2020 - Comments: 1

Chiplet-based exascale computers At the recent IEEE International Electron Devices Meeting (IEDM), CEA-Leti presented a paper on a 3D chiplet technology that enables exascale-level computing systems. The United States and other nations are working on exascale supercomputers. Today’s supercomputers are measured in floating point operations per second. The world’s fastest supercomputers c... » read more

Week In Review: Design, Low Power
By Jesse Allen - 18 Dec, 2020 - Comments: 0

Tools, Cloud, IP Valtrix Systems updated its STING design verification tool for RISC-V based CPU and SoC implementations. Version 1.9.0 adds support to verify recent changes to the RISC-V user and privilege specifications, including draft versions of the vector and bit manipulation standard extensions. Preliminary support for the draft version of the RISC-V hypervisor extension has also been a... » read more

The Darker Side Of Hybrid Bonding
By Katherine Derbyshire - 17 Dec, 2020 - Comments: 2

With semiconductors, it's often things everyone takes for granted that cause the biggest headaches, and that problem is compounded when something fundamental changes — such as bonding two chips together using a process aimed at maximizing performance. Case in point: CMP for backend of the line metallization in hybrid bonding. While this is a mature process, it doesn't easily translate for ... » read more

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