tag: inspection

How Metrology Tools Stack Up In 3D NAND Devices
By Laura Peters - 15 May, 2023 - Comments: 0

Multiple innovations in semiconductor processing are needed to enable 3D NAND bit density increases of about 30% per year at ever-decreasing cost per bit, all of which will be required to meet the nonvolatile storage needs of the big data era. 3D NAND is the first truly three-dimensional device in production. It is both a technology driver for new metrology methods and a significant part of ... » read more

3D Structures Challenge Wire Bond Inspection
By Karen Heyman - 09 May, 2023 - Comments: 1

Adding more layers in packages is making it difficult, and sometimes impossible, to inspect wire bonds that are deep within the different layers. Wire bonds may seem like old technology, but it remains the bonding approach of choice for a broad swath of applications. This is particularly evident in automotive, industrial, and many consumer applications, where the majority of chips are not de... » read more

What Data Center Chipmakers Can Learn From Automotive
By Anne Meixner - 11 Apr, 2023 - Comments: 2

Automotive OEMs are demanding their semiconductor suppliers achieve a nearly unmeasurable target of 10 defective parts per billion (DPPB). Whether this is realistic remains to be seen, but systems companies are looking to emulate that level of quality for their data center SoCs. Building to that quality level is more expensive up front, although ultimately it can save costs versus having to ... » read more

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing
By eBeam Initiative - 15 Mar, 2023 - Comments: 0

Published by the eBeam Initiative Member Companies (February 2023), this list of artificial intelligence (AI) systems used by member companies in their semiconductor manufacturing products shows progress. New examples of systems using AI include: image processing and parameter tuning in lithography tool mask metrology system B-SPline Control Point generation tool sem... » read more

More Accurate And Detailed Analysis of Semiconductor Defects In SEM Images Using SEMI-PointRend
By Technical Paper Link - 10 Mar, 2023 - Comments: 0

A technical paper titled "SEMI-PointRend: Improved Semiconductor Wafer Defect Classification and Segmentation as Rendering" was published (preprint) by researchers at imec, University of Ulsan, and KU Leuven. Abstract: "In this study, we applied the PointRend (Point-based Rendering) method to semiconductor defect segmentation. PointRend is an iterative segmentation algorithm inspired by ima... » read more

Screening For Silent Data Errors
By Anne Meixner - 10 Jan, 2023 - Comments: 0

Engineers are beginning to understand the causes of silent data errors (SDEs) and the data center failures they cause, both of which can be reduced by increasing test coverage and boosting inspection on critical layers. Silent data errors are so named because if engineers don’t look for them, then they don’t know they exist. Unlike other kinds of faulty behaviors, these errors also can c... » read more

Systematic Yield Issues Now Top Priority At Advanced Nodes
By Laura Peters - 06 Dec, 2022 - Comments: 0

Systematic yield issues are supplanting random defects as the dominant concern in semiconductor manufacturing at the most advanced process nodes, requiring more time, effort, and cost to achieve sufficient yield. Yield is the ultimate hush hush topic in semiconductor manufacturing, but it's also the most critical because it determines how many chips can be profitably sold. "At older nodes, b... » read more

Metrology Of Thin Resist For High NA EUVL
By Nova - 16 Nov, 2022 - Comments: 0

One of the many constrains of high numerical aperture extreme ultraviolet lithography (High NA EUVL) is related to resist thickness. In fact, one of the consequences of moving from current 0.33NA to 0.55NA (high NA) is the depth of focus (DOF) reduction. In addition, as the resist feature lines shrink down to 8nm half pitch, it is essential to limit the aspect ratio to avoid pattern collapse. T... » read more

Bump Height Uniformity And 3D Sensing
By Subodh Kulkarni - 08 Nov, 2022 - Comments: 0

Achieving 3D sensing for semiconductor bump height uniformity is essential before adding photoresist. But there are challenges in using traditional methods for measuring uniformity after copper plating, which requires a combination of 3D fringe projection technology and NanoResolution inspection and metrology. Here’s what we’ve learned in a bump height uniformity case study: » read more

Active Learning to Reduce Data Requirements For Defect Identification in Semiconductor Manufacturing
By Technical Paper Link - 24 Oct, 2022 - Comments: 0

A new technical paper titled "Exploring Active Learning for Semiconductor Defect Segmentation" was published by researchers at Agency for Science, Technology and Research (A*STAR) in Singapore. "We identify two unique challenges when applying AL on semiconductor XRM scans: large domain shift and severe class-imbalance. To address these challenges, we propose to perform contrastive pretrainin... » read more

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