Data Centers On Wheels


Automotive architectures are evolving quickly from domain-based to zonal, leveraging the same kind of high-performance computing now found in data centers to make split-second decisions on the road. This is the third major shift in automotive architectures in the past five years, and it's one that centralizes processing using 7nm and 5nm technology, specialized accelerators, high-speed memor... » read more

Week In Review: Manufacturing, Test


Lots more fabs and capacity The chip industry sees opportunity in shortages, and is racing to meet demand. SEMI reports 19 new worldwide high-volume fabs already have started construction, or will start by end of this year, and another 10 are scheduled in 2022. “Equipment spending for these 29 fabs is expected to surpass $140 billion over the next few years as the industry pushes to addre... » read more

Week In Review: Design, Low Power


Synopsys will acquire the semiconductor and flat panel display solutions of BISTel. The acquisition will add an integrated and comprehensive yield management and prediction solution for manufacturing quality and efficiency. BISTel provides engineering equipment systems and AI applications for smart manufacturing in a range of industries. "Combining Synopsys' and BISTel's expertise in fab soluti... » read more

Architectural Considerations For AI


Custom chips, labeled as artificial intelligence (AI) or machine learning (ML), are appearing on a weekly basis, each claiming to be 10X faster than existing devices or consume 1/10 the power. Whether that is enough to dethrone existing architectures, such as GPUs and FPGAs, or whether they will survive alongside those architectures isn't clear yet. The problem, or the opportunity, is that t... » read more

CEO Outlook: More Data, More Integration, Same Deadlines


Experts at the Table: Semiconductor Engineering sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What ... » read more

Bumps Vs. Hybrid Bonding For Advanced Packaging


Advanced packaging continues to gain steam, but now customers must decide whether to design their next high-end packages using existing interconnect schemes or move to a next-generation, higher-density technology called copper hybrid bonding. The decision is far from simple, and in some cases both technologies may be used. Each technology adds new capabilities in next-generation advanced pac... » read more

An Advanced Infrastructure To Enable Secure, Cloud-Aware Design And Processed Data EDA Tool Interoperability


By Rajeev Jain, Kerim Kalafala, and Ramond Rodriguez Significant technology disruptions are on the horizon that will provide massive efficiency gains for EDA tool suppliers and semiconductor companies alike. These disruptions include the application of artificial intelligence and machine learning to enhance supplier tools and optimize user design flows and methodologies, and the ensuing migr... » read more

Week In Review: Manufacturing, Test


Fab tools TEL plans to ship its leading-edge coater/developer system to the joint Imec-ASML research lab, which is working on high-NA extreme ultraviolet (EUV) lithography. The equipment will be integrated with the EXE:5000, ASML’s next-generation high-NA EUV lithography system. The 0.55 numerical aperture (NA) tool is slated to be operational in 2023. Today's EUV is in production, but there... » read more

Week In Review: Design, Low Power


Rambus is making a push for Compute Express Link (CXL) with two acquisitions and the launch of its CXL Memory Interconnect Initiative. The initiative aims to define and develop semiconductor solutions for advanced data center architectures, with initial research and development focusing on solutions to support key memory expansion and pooling use cases. CXL is an open interconnect specificat... » read more

Fan-Out Packaging Options Grow


Chipmakers, OSATs and R&D organizations are developing the next wave of fan-out packages for a range of applications, but sorting out the new options and finding the right solution is proving to be a challenge. Fan-out is a way to assemble one or more dies in an advanced package, enabling chips with better performance and more I/Os for applications like computing, IoT, networking and sma... » read more

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