tag: interconnects

Designing the Right Architecture
By Synopsys - 14 Jan, 2015 - Comments: 0

Designing the right architecture of a multi-processor SoC for today's sophisticated electronic products is a challenging task. The most critical element for meeting the performance requirements of the entire system is the interconnect and memory architecture. These SoC infrastructure IP components are highly configurable and need to be customized to the communication needs of all the other modu... » read more

The Internet Of Cores
By Brian Bailey - 20 Nov, 2014 - Comments: 0

Ever since the birth of the third-party [getkc id="43" comment="IP"] market, there has been a desire for plug-and-play compatibility between cores. Part of the value proposition of reuse is that a block has been used before, and has been verified and validated by having been implemented in silicon. By re-using the core, many of these tasks no longer land on the [getkc id="81" kc_name="SoC"] dev... » read more

Why Investments At Advanced Nodes Matter
By Ed Sperling - 18 Sep, 2014 - Comments: 0

Despite all the talk about rising costs of development, uncertainties about lithography and talk about the death of Moore’s Law, a record number of companies are developing chips at 16nm/14nm. That may sound surprising, but asking why that’s happening is probably the wrong question. The really critical question is what they’re going to do with those chips. What’s become quite evident... » read more

Will 7nm And 5nm Really Happen?
By Mark LaPedus - 14 Jul, 2014 - Comments: 2

Today’s silicon-based finFETs could run out of steam at 10nm. If or when chipmakers move beyond 10nm, IC vendors will require a new transistor architecture. III-V finFETs, gate-all-around FETs, quantum well finFETs, SOI finFETs and vertical nanowires are just a few of the future transistor candidates at 7nm and 5nm. Technically, it’s possible to manufacture the transistor portions of the... » read more

Blog Review: June 25
By Ed Sperling - 25 Jun, 2014 - Comments: 0

Is the Amazon Fire smart phone a paradigm shift? Cadence’s Brian Fuller looks at the first application-specific smart phone and why it’s noteworthy—regardless of how well it fares against phones made by Apple and Samsung. Rambus’ Deepak Chandra Sekar digs deep into interconnect technology and where the prevailing winds are blowing—copper barrier/cap/liner optimization, a slowdown i... » read more

Executive Insight: Simon Segars
By Ed Sperling - 03 Jun, 2014 - Comments: 0

SE: What concerns you most? Segars: In the context of design and where chip design is going, ARM is a long-term business. We’re doing stuff now that is going to ship in five years’ time. Obviously, for everyone in this space, Moore’s Law has been a fantastic thing. It’s enabled us to achieve really fantastic scaling of transistors, and everyone knows that is getting harder and harder... » read more

New Materials Era In Advanced Interconnects
By Kavita Shah - 15 May, 2014 - Comments: 0

By Kavita Shah Growth in semiconductors today is driven primarily by mobile applications and this demand continues to increase with no slowdown in sight. Supporting this trend, chipmakers continue adding smaller and faster transistors to chips to maintain the pace of Moore’s Law, and as a consequence copper wiring is being drastically scaled and densities increased. Today advanced chips c... » read more

Atomic Layer Etch Finally Emerges
By Mark LaPedus - 15 May, 2014 - Comments: 1

The migration towards finFETs and other devices at the 20nm node and beyond will require a new array of chip-manufacturing technologies. Multiple patterning, hybrid metrology and newfangled interconnect schemes are just a few of the technologies required for future scaling. In addition, the industry also will require new techniques that can process structures at the atomic level. For example... » read more

The Bumpy Road To FinFETs
By Mark LaPedus - 15 May, 2014 - Comments: 2

The shift from planar transistors to finFETs is a major inflection point in the IC industry. FinFETs are expected to enable higher performance chips at lower voltages. And the next-generation transistor technology also could allow the industry to extend CMOS to the 10nm node and perhaps beyond. But as it turns out, finFET technology is also harder to master than previously thought. For exam... » read more

Interconnect Challenges Grow
By Mark LaPedus - 20 Feb, 2014 - Comments: 0

Qualcomm outlined the technology challenges facing mobile chip suppliers at a recent event. In no particular order, the challenges include the usual suspects—area scaling, power reduction, performance and cost. Another concern for Qualcomm is an often-overlooked part of the equation—the backend-of-the-line (BEOL). In chip production, the BEOL is where the interconnects are formed within ... » read more

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