tag: interposers

The Race Toward Mixed-Foundry Chiplets
By Ann Mutschler - 23 Mar, 2023 - Comments: 1

Creating chiplets with as much flexibility as possible has captured the imagination of the semiconductor ecosystem, but how heterogeneous integration of chiplets from different foundries will play out remains unclear. Many companies in the semiconductor ecosystem are still figuring out how they will fit into this heterogeneous chiplet world and what issues they will need to solve. While near... » read more

Improving Performance And Power With HBM3
By Andy Patrizio - 30 Jan, 2023 - Comments: 0

HBM3 swings open the door to significantly faster data movement between memory and processors, reducing the power it takes to send and receive signals and boosting the performance of systems where high data throughput is required. But using this memory is expensive and complicated, and that likely will continue to be the case in the short term. High Bandwidth Memory 3 (HBM3) is the most rece... » read more

What Does 2023 Have In Store For Chip Design?
By Brian Bailey - 26 Jan, 2023 - Comments: 0

Predictions seem to be easier to make during times of stability, but they are no more correct than at any other period. During more turbulent times, fewer people are courageous enough to allow their opinions to be heard. And yet it is often those views that are more well thought through, and even if they turn out not to be true, they often contain some very enlightening ideas. 2022 saw some ... » read more

Choosing The Correct High-Bandwidth Memory
By Ann Mutschler - 25 Jan, 2023 - Comments: 0

The number of options for how to build high-performance chips is growing, but the choices for attached memory have barely budged. To achieve maximum performance in automotive, consumer, and hyperscale computing, the choices come down to one or more flavors of DRAM, and the biggest tradeoff is cost versus speed. DRAM remains an essential component in any of these architectures, despite years ... » read more

Multi-Die Integration
By Ed Sperling - 04 Jan, 2023 - Comments: 0

Putting multiple heterogeneous chips is the way forward for improved performance and more functionality, but it also brings a host of new challenges around partitioning, layout, and thermal. Michael Posner, senior director for die-to-die connectivity at Synopsys, talks about the advantages of 3D integration, why it’s finally going mainstream, and what’s needed in the EDA tools to make this ... » read more

Designing For Multiple Die
By Ann Mutschler - 21 Dec, 2022 - Comments: 1

Integrating multiple die or chiplets into a package is proving to be very different than putting them on the same die, where everything is developed at the same node using the same foundry process. As designs become more heterogeneous and disaggregated, they need to be modeled, properly floor-planned, verified, and debugged in the context of a system, rather than as individual components. Typi... » read more

Heterogeneous Integration Issues And Developments
By Ed Sperling - 14 Dec, 2022 - Comments: 0

There are a slew of new developments in advanced packaging, from new materials, chiplets, and interconnect schemes, to challenges involving how to physically put chips in a package, metallization, thermal cycling, and parasitics in the interconnect path. Dick Otte, CEO of Promex Industries, talks about how this will change chip design and manufacturing, and how those changes are likely to unfol... » read more

3D-IC Reliability Degrades With Increasing Temperature
By Ann Mutschler - 14 Dec, 2022 - Comments: 0

The reliability of 3D-IC designs is dependent upon the ability of engineering teams to control heat, which can significantly degrade performance and accelerate circuit aging. While heat has been problematic in semiconductor design since at least 28nm, it is much more challenging to deal with inside a 3D package, where electromigration can spread to multiple chips on multiple levels. “Be... » read more

The Computational Electromagnetics Simulation Challenge Of 3D-IC
By Kelly Damalou - 29 Nov, 2022 - Comments: 0

By Kelly Damalou and Matt Commens Innovation in semiconductor design today is energized primarily by AI/ML, data centers, autonomous and electric vehicles, 5G/6G, and IoT. Recently developed 2.5 and 3D-IC silicon-based packaging technologies have advanced the state of the art beyond SoC technologies which first united digital, analog, and memory functions on a single chip in the '90s. These ... » read more

Is UCIe Really Universal?
By Brian Bailey - 22 Nov, 2022 - Comments: 3

Chiplets are rapidly becoming the means to overcome the slowing of Moore's Law, but whether one interface is capable of joining them all together isn't clear yet. The Universal Chiplet Interconnect Express (UCIe) believes it will work, but some in the industry remain unconvinced. At least part of the problem is that interconnect standards are never truly finished. Even today, the protocols tha... » read more

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