tag: IP reuse

The Limits Of IP Reuse
By Ed Sperling - 07 Sep, 2017 - Comments: 0

The basic business proposition for third-party IP is that it's cheaper, faster, and less problematic to buy rather than build. But things haven't exactly worked out according to plan, either for companies that license IP or those that develop it. For [getkc id="43" kc_name="IP"] licensees, just keeping track of an endless series of updates is becoming unwieldy. Complex designs often include ... » read more

IP Business Changing As Markets Shift
By Ed Sperling - 03 Aug, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss IP protection, tracking and reuse with Srinath Anantharaman, CEO of [getentity id="22203" e_name="ClioSoft"]; and Jeff Galloway, CTO of Silicon Creations; Marc Greenberg, group director of product marketing for [getentity id="22032" e_name="Cadence"]'s IP Group; and John Koeter, vice president of marketing for [getentity id="22035" e_name="Synopsys"... » read more

Re-Using IP In Packaging
By Ed Sperling - 10 Jul, 2017 - Comments: 0

For the past decade, the promise held forth by advanced packaging was that it would allow chipmakers to mix and match analog and digital IP without worrying about the process node at which they were developed or the physical interactions between components. This is a big deal when it comes to analog. Analog IP doesn't benefit from node shrinking the way digital logic does, and in many cases ... » read more

Verification Facing Unique Inflection Point
By Brian Bailey - 10 Mar, 2016 - Comments: 0

The Design and Verification Conference and Exhibition (DVCon) attracted more than 1,100 people to San Jose last week, just slightly less than last year. While a lot of focus, and most of the glory, goes to design within semiconductor companies, it is verification where most of the advancements are happening and thus the bigger focus for DVCon. The rate of change in verification and the producti... » read more

Powerful New Standard
By Brian Bailey - 02 Mar, 2016 - Comments: 1

In December 2015, the IEEE released the latest version of the 1801 specification, titled the IEEE standard for design and verification of low-power integrated circuits, but most people know it as UPF or the Unified Power Format. The standard provides a way to specify the power intent associated with a design. With it, a designer can define the various power states of the design and the contexts... » read more

Bridging Hardware And Software
By Ann Mutschler - 18 Jan, 2016 - Comments: 1

Methodology and reuse are two fairly standard concepts when it comes to semiconductor design, but they're viewed completely differently by hardware and software teams. It's a given that hardware and software have different goals and opinions about how best to do design. And while all agree that a single methodology can pay dividends in future chips, there is disagreement over who should shap... » read more

The Beginning
By Anupam Bakshi - 22 Dec, 2015 - Comments: 0

We all want our creations to transcend time. Our products, our designs—even our specifications. Specifications are more than just ideas or collections of requirements or static collections of implementation details. They live inside many chips and many designs, and the more flexible and portable they are, the longer they remain relevant. End devices may be replaced relatively quickly, but ... » read more

A New Reuse Paradigm To Take 2.5D Packaging Technology Mainstream
By Jeff Scott - 23 Oct, 2014 - Comments: 0

With all of the recent product implementations and demonstrations of the technical viability of 2.5D technology, there is a lot of excitement around its potential. However, as with any new technology, there are concerns with cost and risk that limit mainstream adoption. Cost reduction and risk mitigation require some level of volume production, and therein lies a classic Catch-22. Is there a wa... » read more

Platforms, Standards, Methodologies Conquer Design Challenges
By Brian Fuller - 10 Apr, 2014 - Comments: 0

We in the electronics design world always have spent a lot of time wringing our hands (will we ever get to design below 1 micron??) And while the problems are not imagined—they’re often soberingly real—we tend to plow through them, or, when necessary around them. Today, amid increasing complexity and risk, we’re leveraging platforms, standards and new methodologies to slay these d... » read more

2014 Accellera Standards Are Built on Powerful Shoulders
By Accellera - 27 Jan, 2014 - Comments: 0

By Adam Sherer Looking out at the fresh snow coating the landscape here in Buffalo, it’s tempting to look toward 2014 and focus only on the fresh and new. However, if I’ve learned anything about this city from the day I arrived here as a freshman EE in 1984, it’s that you don’t bury your foundation. Instead, you recognize it as your greatest strength, the powerful shoulders upon whic... » read more

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