Enabling The RISC-V Ecosystem

By Tom Anderson - 27 Jun, 2019 - Comments: 0

Earlier this year, OneSpin’s Sven Beyer discussed the emerging RISC-V processor and some of its verification challenges. He stated that “RISC-V is hot and stands at the beginning of what may be a major shift in the industry.” In the few intervening months, it has become even more apparent that RISC-V is fundamentally changing system-on-chip (SoC) development. Dozens of commercial and open... » read more

Complete Formal Verification of RISC V Processor IPs for Trojan-Free Trusted ICs

By OneSpin Solutions - 26 Jun, 2019 - Comments: 0

RISC-V processor IPs are increasingly being integrated into system-on-chip designs for a variety of applications. However, there is still a lack of dedicated functional verification solutions supporting high-integrity, trusted integrated circuits. This paper examines an efficient, novel, formal-based RISC-V processor verification methodology. The RISC-V ISA is formalized in a set of Operational... » read more

The 7nm Pileup

By Ed Sperling - 04 Apr, 2019 - Comments: 1

The number of 7nm designs is exploding. Cadence alone reports 80 new 7nm chips under design. So why now, and what does this all mean? First of all, 7nm appears to be the next 28nm. It's a major node, and it intersects with a number of broad trends that are happening across the industry, all of which involve AI in one way or another. The big question now is how many of them will survive long ... » read more

Designing An AI SoC

By Ed Sperling - 11 Mar, 2019 - Comments: 0

Susheel Tadikonda, vice president of networking and storage at Synopsys, looks at how to achieve economies of scale in AI chips and where the common elements are across all the different architectures. https://youtu.be/fm0kxnj3DuM » read more

The Challenge Of RISC-V Compliance

By Brian Bailey - 28 Feb, 2019 - Comments: 0

The open-source RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure that ecosystem development works for all implementations and that all cores that ... » read more

Beyond The RISC-V ISA

By Gajinder Panesar - 20 Dec, 2018 - Comments: 1

For chip architects and designers today, “the ISA” in RISC-V is a small consideration. The concern isn’t even choosing “the core.” Designers today are faced by a “whole system” problem—a problem of systemic complexity. That fact is implicit in the picture that I show people to explain the UltraSoC embedded analytics architecture. It shows a block-level representation of an So... » read more

Designing An Efficient DSP Solution

By Synopsys - 13 Jul, 2016 - Comments: 0

A look at the key challenges in DSP implementation from both hardware and software application perspectives, and how a properly selected and configured DSP processor coupled with an advanced software development toolchain can overcome these challenges. This white paper describes how to generate tight, efficient, and maintainable DSP code for a platform consisting of an IP core based on a specia... » read more

Alternative To x86, ARM Architectures?

By Jeff Dorsch - 07 Jun, 2016 - Comments: 1

Software developed by professors and graduate students from the University of California at Berkeley? That will never fly in the semiconductor industry, right? Maybe they said that about SPICE, four decades ago. The jury is still out on RISC-V (pronounced risk-five) the modular, open-source instruction set architecture created in this decade by Cal professors and students, yet the ISA is gai... » read more

Lightweight Cryptography For The IoE

By Ernest Worthman - 03 Sep, 2015 - Comments: 0

This is the age where technology is expected to do more, faster, anonymously, and often invisibly. And it's supposed to use less power, with smaller footprints, unobtrusively and intuitively. And all that needs to be protected with cryptography. That's the goal, at least. But as Simon Blake-Wilson, vice president of products and marketing for [getentity id="22671" e_name="Rambus"]' Cryptogra... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: ISA