Week In Review: Manufacturing, Test


Onshoring and the supply chain Efforts to patch up supply chain weaknesses by moving more manufacturing onshore in the United States and Europe are generating a lot of buzz. Morris Chang, TMSC's founder, described those moves as "a very expensive exercise in futility," during an interview with the Brookings Institution and Center for Strategic and International Studies, adding that it is like... » read more

Photomask Shortages Grow At Mature Nodes


A surge in demand for chips at mature nodes, coupled with aging photomask-making equipment at those geometries, are causing significant concern across the supply chain. These issues began to surface only recently, but they are particularly worrisome for photomasks, which are critical for chip production. Manufacturing capacity is especially tight for photomasks at 28nm and above, driving up ... » read more

Equipment Perspective At U.S. Senate Hearing On Chipmaking


In March, Lam Research President and CEO Tim Archer testified before the United States Senate Committee on Commerce, Science, and Transportation. The hearing examined a variety of issues including the correlation between American competitiveness and semiconductors, the impact of vulnerabilities in semiconductor supply chains and the importance of CHIPS legislation within the U.S. Innovation a... » read more

Strategies For Faster Yield Ramps On 5nm Chips


Leading chipmakers TSMC and Samsung are producing 5nm devices in high volume production and TSMC is forging ahead with plans for first 3nm silicon by year end. But to meet such aggressive targets, engineers must identify defects and ramp yield faster than before. Getting a handle on EUV stochastic defects — non-repeating patterning defects such as microbridges, broken lines, or missing con... » read more

Week In Review: Manufacturing, Test


Deals AMD plans to purchase cloud startup Pensando for about US $1.9 billion. In a presentation at the SEMI ISS conference this week, AMD CTO Mark Papermaster described Pensando's technology as a "highly programmable packet-processing engine that allows you to speed up systems designed for the data center." Intel, Micron, Analog Devices and MITRE Engenuity formed an alliance to accelerate c... » read more

Week In Review: Manufacturing, Test


Worldwide fab equipment spending for front-end manufacturing is expected to hit $107 billion this year, an 18% year-over-year increase, according to SEMI’s latest World Fab Forecast report. “Crossing the $100 billion mark in spending on global fab equipment for the first time is a historic milestone for the semiconductor industry,” said Ajit Manocha, president and CEO of SEMI. Investme... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive Suzuki will collaborate with SkyDrive on flying cars. SkyDrive is working on an air taxi service that it wants to launch at the 2025 World Exposition in Osaka, Japan. Recalls: The car company Tesla is recalling 947 vehicles in the United States because rearview image lags and does not display immediately when the car is put into reverse, said the National Highway Traffic Safety A... » read more

Highly Selective Etch Rolls Out For Next-Gen Chips


Several etch vendors are starting to ship next-generation selective etch tools, paving the way for new memory and logic devices. Applied Materials was the first vendor to ship a next-gen selective etch system, sometimes called highly-selective etch, in 2016. Now, Lam Research, TEL, and others are shipping tools with highly-selective etch capabilities, in preparation for futuristic devices su... » read more

Week In Review: Manufacturing, Test


Chipmakers, OEMs Intel continues to build more fabs. First, the company announced fabs in Arizona and then Ohio. Now, Intel plans to invest up to €80 billion in the European Union over the next decade. As part of the effort, Intel plans to build two semiconductor fabs in Magdeburg, Germany. Construction is expected to begin in the first half of 2023 and production planned to come online in 2... » read more

Extending Copper Interconnects To 2nm


Transistor scaling is reaching a tipping point at 3nm, where nanosheet FETs will likely replace finFETs to meet performance, power, area, and cost (PPAC) goals. A significant architectural change is similarly being evaluated for copper interconnects at 2nm, a move that would reconfigure the way power is delivered to transistors. This approach relies on so-called buried power rails (BPRs) and... » read more

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