tag: Leti

Chip Industry Technical Paper Roundup: Sept. 24
By Linda Christensen - 24 Sep, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=358 /] More ReadingTechnical Paper Library home » read more

Better Security and Power Efficiency of Ascon HW Implementation with STT-MRAM (CEA, et al.)
By Technical Paper Link - 18 Sep, 2024 - Comments: 0

A new technical paper titled "Enhancing Security and Power Efficiency of Ascon Hardware Implementation with STT-MRAM" was published by researchers at CEA, Leti, Université Grenoble Alpes, CNRS, and Spintec. Abstract "With the outstanding growth of Internet of Things (IoT) devices, security and power efficiency of integrated circuits can no longer be overlooked. Current approved standards f... » read more

Chip Industry Technical Paper Roundup: March 26
By Linda Christensen - 26 Mar, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library. [table id=209 /] Find last week's technical paper additions here. » read more

Predicting Warpage in Different Types of IC Stacks At Early Stage Of Package Design
By Technical Paper Link - 15 Mar, 2024 - Comments: 0

A new technical paper titled "Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects" was published by researchers at Siemens EDA, D2S, and Univ. Grenoble Alpes, CEA, Leti. Abstract: "A physics-based multi-scale simulation methodology that analyses die stress variations generated by package fabrication is employed for warpage study. The ... » read more

Chip Industry Technical Paper Roundup: Jan 2
By Linda Christensen - 02 Jan, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=180 /] More ReadingTechnical Paper Library home » read more

Memory Devices-Based Bayesian Neural Networks For Edge AI
By Technical Paper Link - 20 Dec, 2023 - Comments: 0

A new technical paper titled "Bringing uncertainty quantification to the extreme-edge with memristor-based Bayesian neural networks" was published by researchers at Université Grenoble Alpes, CEA, LETI, and CNRS. Abstract: "Safety-critical sensory applications, like medical diagnosis, demand accurate decisions from limited, noisy data. Bayesian neural networks excel at such tasks, offering... » read more

Week In Review: Semiconductor Manufacturing, Test
By Susan Rambo - 30 Jun, 2023 - Comments: 0

Restrictions on China continue to grow. The Biden Administration is considering more restrictions on selling advanced AI chips to China, according to multiple media reports. Meanwhile, the Dutch government is expected to limit the sale of manufacturing equipment. JIC Capital, the wholly owned subsidiary of Japan Investment Corporation (JIC), will purchase materials company JSR Corp. through ... » read more

Chip Industry’s Technical Paper Roundup: Apr. 18
By Linda Christensen - 18 Apr, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=93 /]   If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involv... » read more

Vertical Nanowire Gate-All-Around FETs based on the GeSn-Material System Grown on Si
By Technical Paper Link - 10 Apr, 2023 - Comments: 0

A new technical paper titled "Vertical GeSn nanowire MOSFETs for CMOS beyond silicon" was published by researchers at Peter Grünberg Institute 9, JARA, RWTH Aachen University, CEA, LETI, University of Grenoble Alpes, University of Leeds, and IHP. "Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET transcon... » read more

The March Toward Chiplets
By Ed Sperling and Karen Heyman - 15 Dec, 2022 - Comments: 0

The days of monolithic chips developed at the most advanced process nodes are rapidly dwindling. Nearly everyone working at the leading edge of design is looking toward some type of advanced packaging using discrete heterogeneous components. The challenge now is how to shift the whole chip industry into this disaggregated model. It's going to take time, effort, as well as a substantial reali... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy