Improving EUV Process Efficiency

By Mark LaPedus - 19 Mar, 2020 - Comments: 2

The semiconductor industry is rethinking the manufacturing flow for extreme ultraviolet (EUV) lithography in an effort to improve the overall process and reduce waste in the fab. Vendors currently are developing new and potentially breakthrough fab materials and equipment. Those technologies are still in R&D and have yet to be proven. But if they work as planned, they could boost the flo... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 28 Feb, 2020 - Comments: 2

SPIE At the SPIE Advanced Lithography conference, Lam Research has introduced a new dry resist technology for extreme ultraviolet (EUV) lithography. Dry resist technology is a new approach to deposit and develop EUV resists. It is a dry deposition technique with alternate compositions and mechanisms. By combining Lam’s deposition and etch process expertise with partnerships with ASML a... » read more

Extreme Quality Semiconductor Manufacturing

By Ben Tsai - 11 Feb, 2020 - Comments: 0

By Ben Tsai and Cathy Perry Sullivan Across the full range of semiconductor device types and design nodes, there is a drive to produce chips with significantly higher quality. Automotive, IoT and other industrial applications require chips that achieve very high reliability over a long period of time, and some of these chips must maintain reliable performance while operating in an environmen... » read more

Finding Defects In EUV Masks

By Mark LaPedus - 23 Jan, 2020 - Comments: 0

Extreme ultraviolet (EUV) lithography is finally in production at advanced nodes, but there are still several challenges with the technology, such as EUV mask defects. Defects are unwanted deviations in chips, which can impact yield and performance. They can crop up during the chip manufacturing process, including the production of a mask or photomask, sometimes called a reticle. Fortunately... » read more

Multi-Patterning EUV Vs. High-NA EUV

By Mark LaPedus - 04 Dec, 2019 - Comments: 4

Foundries are finally in production with EUV lithography at 7nm, but chip customers must now decide whether to implement their next designs using EUV-based multiple patterning at 5nm/3nm or wait for a new single-patterning EUV system at 3nm and beyond. This scenario revolves around ASML’s current extreme ultraviolet (EUV) lithography tool (NXE:3400C) versus a completely new EUV system with... » read more

Making And Protecting Advanced Masks

By Mark LaPedus - 27 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

Planning For Panel-Level Fan-out

By Mark LaPedus - 21 Nov, 2019 - Comments: 0

Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

Using Digital Twins And DL In Lithography

By Ed Sperling - 21 Nov, 2019 - Comments: 0

Leo Pang, chief product officer and executive vice president at D2S, looks at the results of inverse lithography technology at advanced nodes using curvilinear patterns, and how that can be combined with a digital twin and deep learning speed up time to market and reduce cost. » read more

Inspecting, Patterning EUV Masks

By Mark LaPedus - 06 Nov, 2019 - Comments: 0

What’s The Best Advanced Packaging Option?

By Mark LaPedus - 17 Oct, 2019 - Comments: 2

As traditional chip designs become more unwieldy and expensive at each node, many IC vendors are exploring or pursuing alternative approaches using advanced packaging. The problem is there are too many advanced packaging options on the table already, and the list continues to grow. Moreover, each option has several tradeoffs and challenges, and all of them are still relatively expensive. ... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: lithography