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AI And High-NA EUV At 3/2/1nm

EUV double patterning likely at 3nm; what comes after that is uncertain.

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Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To view part one of this discussion, click here. Part two is here.

SE: For decades, the IC industry has followed the Moore’s Law axiom that transistor density in chips doubles every 18 to 24 months. At this cadence, chipmakers can pack more and smaller transistors on a die. But Moore’s Law is slowing down. Any thoughts?

Fujimura: D2S is a software supplier to the semiconductor manufacturing industry specializing in GPU acceleration, which couples the computing powers of both CPUs and GPUs. So we’re a good example of a consumer of computing power. We feel every day that there’s so much more we can do to help manufacturing if we had more computing power per dollar. This was already true with scientific computing, like what we do, but what broke the dam was deep learning. I would be surprised if there was a Fortune 500 company that isn’t heavily investing in deep learning one way or another. There has been a bifurcation in the chip industry where supercomputing needs, including deep learning, are driving an insatiable demand for more and more computing power that will come from 3nm, 2nm, and beyond. Meanwhile, IoT and other high-volume, low-cost applications will continue to use the trailing edge.

Levinson: What really worries me the most about extending technology is not patterning. It’s the devices and the interconnect. There, nobody really has a solution. In lithography, we at least have multiple solutions, and now we have the luxury of choosing from them. I worry a lot about the devices. And that can delay things.

SE: Today, chipmakers are using extreme ultraviolet (EUV) lithography with single patterning techniques. But at some point, EUV single patterning will reach the limit. Then, chipmakers must go to EUV double patterning or wait for high-NA EUV. (Today’s EUV lithography scanners incorporate a 0.33 numerical aperture lens, while high-NA lithography utilizes a 0.55 NA lens. Still in R&D, the first high-NA EUV tool is expected in 2022.) How will this play out?

Levinson: The good news is that chipmakers have stopped asking the resist suppliers for 20mJ/cm2 resists, which was preventing the extension of 0.33 NA EUV lithography toward its resolution limits. So we’re seeing a lot of progress now in EUV resists. We will see an extension of single patterning 0.33 NA EUV for the 5nm node. But then the question is, what do you do after that? The next node is 3nm, or whatever you call it. That will be developed using 0.33 NA EUV double patterning. That is simply because of the timeline of bringing a new exposure tool like high-NA to maturity. And then, when you go to manufacturing, then maybe you go to high-NA EUV. It’s one of those things where you just have to wait and see. It can go either way. The good news is we have solutions.

Nakayamada: High-NA will not be used for the 3nm node. 3nm may be done using EUV with double or quadruple patterning.

SE: Is EUV double patterning expensive and difficult?

Levinson: If it’s just double patterning, it will be acceptable. You will get enough of a shrink to justify it. We will need very good process control. In optical patterning, we don’t just do double patterning. We have these multiple cut layers and things like that. And that’s not just because of resolution. It’s also because of process control. And so you do these self-aligned blocks and things like that. There was a recent Imec presentation with a 2nm pitch technology made with EUV multiple patterning. It requires quadruple patterning for the metal layers.

Kasprowicz: What’s the alternative besides EUV double patterning here? I don’t believe there are any, so you’re going to have do it to advance to the next node. Besides, the rumored $250 million for a high-NA scanner is a pretty steep price tag to anyone. And experience tells us that it takes time to evaluate, qualify and integrate new tools, regardless of technology. I would guess that the first high-NA tools to each company are going to take a while to get inducted into any kind of manufacturing environment. From there, my guess is that you’ll see increased usage, but likely not as quickly as the 0.33 NA tools simply because of cost.

Levinson: With EUV double patterning it’s not that big of a deal. But there will have to be work done on the process control side. So we’ll need multi-beam writers to make excellent masks. We’ll need all of ILT (inverse lithography technology) schemes to squeeze every little bit of process capability out and so forth. People will figure it out.

SE: What are the challenges for high-NA EUV?

Levinson: Fortunately, a lot of the issues are just very foundational. Zeiss and ASML have moved up the learning curve. But one of the things that worries me about high-NA is the need for much greater improvements in EUV resists. In addition, the depth-of-focus for high-NA EUV lithography will only be about 1/3 of that for 0.33 NA EUV lithography, necessitating very good focus control. The high tool prices, coupled with the impact of half-size exposure fields on throughput, will make wafer costs a continuing concern. Also, with the current unpolarized light sources, there is image contrast loss at 0.55 NA. None of these issues is insurmountable, but they will keep lithographers busy.

Fujimura: The need to split a full reticle design into two halves, with sufficient space in between them, adds an extra constraint to how these chips need to be designed. It isn’t possible to stitch the two halves written with different masks perfectly, so the two halves need to be physically separated by some distance during physical design, with the chip designers knowing that a particular layer is going to be written with high-NA. It’s also the case that 1/9th the reticle size in a 3 x 3 array of a chip would not be practical. Therefore, there will be a little more constraint on the physical design of chips with high-NA. However, these devices at the leading-edge nodes are so complex that there are a lot of repeated structures on the design. There’s a human organizational limitation on what can reasonably be designed and verified in reasonable time, and full reticle designs will need redundancy to get reasonable yield. So there are natural partitions in the physical design. Also, high-NA layers are the critical layers, so stitching with interconnect in layers that aren’t written with high-NA won’t be a problem. High-NA does add a constraint to the design, but designers will find clever ways to deal with it.

Kasprowicz: The high-NA tool will have different imaging optics, namely it is anamorphic — implying that one axis is 4X and the other is 8X, versus being the same in both axis for all previous generations. So in reference to the mask maker working through the typical mask process flow, there are a number of unknowns, such as data preparation. Currently, we provide the hierarchical data and then support layout and fracture. With the anamorphic lens, the OPC (optical proximity correction) will change once the scaling is applied. The data verification step is not straightforward. The angles created by the OPC and dual scaling will create angles that, amongst other reasons, will dictate that a multi-beam mask writing patterning tool is required. Furthermore, there is inspection, mainly defect disposition methods. Will the inspection tools have the capability to emulate the scanner so potential defects are identified and further characterized by an AIMS inspection system or other methods? If not, then complex techniques may be required to provide this assessment. All of these take time and require investment for the proper tooling, which in turn drives overall mask cost.

SE: Today’s EUV masks consist of 40 to 50 alternating layers of silicon and molybdenum on top of a substrate, resulting in a multi-layer stack that is 250nm to 350nm thick. On the stack, there is a ruthenium-based capping layer, followed by an absorber based on tantalum. Today’s EUV masks suffer from so-called mask 3D effects, which could cause unwanted pattern placement shifts. So at 3nm and beyond, the industry may need new types of EUV masks, right?


Fig. 1: Cross-section of an EUV mask. In EUV, light hits the mask at an angle of 6°. Source: Luong, V., Philipsen, V., Hendrickx, E., Opsomer, K., Detavernier, C., Laubis, C., Scholze, F., Heyns, M., “Ni-Al alloys as alternative EUV mask absorber,” Appl. Sci. (8), 521 (2018). Imec, KU Leuven, Ghent University, PTB

Kasprowicz: Some are starting to look at attenuated phase-shift EUV masks and high-k EUV masks, even for today’s 0.33 NA EUV scanners. While we have gained vast experience in validating the current tantalum-based materials, validating new materials will take time. And a bigger question is, will the industry harmonize like it did with tantalum, or are there going to be many different types of EUV masks depending on the product type (memory versus logic)? Another concern is, will we get adequate reflectance off of the multi-layer structure using the standard Mo/Si multi-layer EUV mask blank for high-NA? If not, then a fair effort may be required to look at the alternate options for the multi-layer blank. The decision to develop different EUV mask types depends on how much effort is going to be required and what the right mixture is going to be to create these new EUV mask types. It also depends how much inter-layer diffusion will happen as you expose these blanks over time. You also may not need as many multi-layer pairs with these next-generation EUV blanks, because it will be a stronger mirror. There are a lot of things that are unknown yet. And the blank makers are looking at all the factors. Once again, in R&D, there is the development of high-k and phase-shift EUV masks for the 0.33 NA EUV tools. That’s where the focus is right now. In the background, many are looking at some of the different multi-layer propositions, as well. No matter what is deposited on it, the mask makers must be able to pattern it. We have to be able to remove or etch it. We have to be able to inspect it and deliver the product in the end.

SE: To some degree, several chipmakers are deploying machine learning techniques in the fab and the mask shop for defect detection and other apps. Will we ever see widespread deployment of deep learning in mask making?

Fujimura: In the eBeam Initiative’s Luminaries Survey, we asked a question on that subject. About two thirds of the people believe that some kind of deep learning will be deployed somewhere in the mask-making process by 2022. Some people thought that maybe sometime in 2023, and some people thought it would never be used. The opinions are not as uniform as if you had asked this question: ‘Would deep learning be deployed in autonomous driving?’ My personal thought is that deep learning will start to get deployed in mask making soon. Just to reiterate, deep learning is a particular version of machine learning. Machine learning prior to deep learning has already been used, particularly in analyzing big data. Fabs and mask shops have big data. But deep learning enables a whole new set of possibilities for helping to manufacture better and faster. For example, in the process of doing ILT, you can speed up the processing quite a bit — around 2X or more. It can also improve accuracy by making fast estimations of effects that would otherwise be too compute-intensive to incorporate. Multiple papers have been published on the use of deep learning for mask 3D effect compensation, for example. In addition, because deep learning is so evolved in image processing, applications that automatically analyze SEM images or automatically categorize defects detected by inspection will be deployed in mask shops. Deep learning has a trap in that it is easy to prototype, but requires tremendous amounts of data to make it production quality. Just as the autonomous driving community has found, digital twins that generate data, like an image of a child chasing a balloon or an image of a particularly tricky type of a defect, are critical. You don’t need them for a prototype to show promising results. But you must have them for production deployment of deep learning.

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