tag: low-k

Extracting Intrinsic Mechanical Properties Of Thin Low-Dielectric Constant Materials With iTF Analysis
By Bruker - 12 Apr, 2022 - Comments: 0

This white paper focuses on the optimization and use of Bruker’s iTF software package for the extraction of intrinsic (substrate independent) mechanical properties, particularly for thin, low-k materials. These considerations are split into two main parts: Measurement procedure (Section II) and iTF execution (Section III). The former outlines important aspects of acquiring proper experimental... » read more

Evaluation Of The Impact Of Source Drain epi Implementation On Logic Performance Using Combined Process And Circuit Simulation
By Coventor - 17 Feb, 2021 - Comments: 0

In this paper, we explore an end-to-end solution using SEMulator3D to address the need to include process variation effects in circuit simulation. For the first time, we couple SEMulator3D with BSIM compact modeling to evaluate process variation impacts on circuit performance. The process integration goal of the study was to optimize contacts and spacer thickness of advanced-node FinFETs in ter... » read more

Dealing With Resistance In Chips
By Mark LaPedus - 21 Jun, 2018 - Comments: 2

Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects. That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resist... » read more

New BEOL/MOL Breakthroughs?
By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

Inside Inspection And Metrology
By Mark LaPedus - 18 Dec, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about inspection, metrology and other issues with Mehdi Vaez-Iravani, vice president of advanced imaging technologies at Applied Materials. What follows are excerpts of that conversation. SE: Today, the industry is working on a new range of complex architectures, such as 3D NAND and finFETs. For these technologies, the industry is clearly struggling... » read more

Dealing With Atoms
By Mark LaPedus - 13 Jul, 2015 - Comments: 0

Chipmakers are ramping up a new range of device architectures, such as 3D NAND and finFETs. But to enable current and future devices, IC vendors will require new breakthroughs, including tools that can process tiny structures and films, even at the atomic level. The problem? There are gaps in terms of techniques that can process chips at the atomic level. Looking to help fill part of the ... » read more

Addressing Thin Film Thickness Metrology Challenges Of 14nm BEOL Layers
By KLA - 21 May, 2015 - Comments: 0

This paper describes a method to effectively monitor the film stack at different metal CMP process steps using a spectroscopic ellipsometer metrology tool. By proper modeling of the Cu dispersion and simulating the underlayer film information underneath the Cu pad, a single measurement recipe was developed which can be used to monitor each process step in the metal CMP process with stable and r... » read more

One-On-One: Dark Possibilities
By Katherine Derbyshire - 29 Apr, 2015 - Comments: 0

Professor Michael Taylor’s research group at UC San Diego is studying ways to exploit dark silicon to optimize circuit designs for energy efficiency. He spoke with Semiconductor Engineering about the post-Dennard scaling regime, energy efficiency from integrated circuits all the way up to data centers, and how the manufacturing side can help. What follows are excerpts of that conversation. (P... » read more

Will Materials Derail Moore’s Law?
By Mark LaPedus - 13 Nov, 2014 - Comments: 0

Is Moore’s Law slowing down? Clearly, chipmakers are struggling to keep up with Moore’s Law these days. But one sometimes forgotten and critical technology could easily derail Moore’s Law--materials. In fact, the cost and complexity for electronic materials are increasing at each node. “Chemical and gas commodity procurement spends are growing rapidly due to process complexity and un... » read more

Manufacturing Bits: July 16
By Mark LaPedus - 16 Jul, 2013 - Comments: 0

Photon Chips Harvard University, the Massachusetts Institute of Technology (MIT) and the Vienna University of Technology have devised an all-optical transistor controlled by a single photon. The optical transistor could enable the development of photonic quantum gates and deterministic multi-photon entanglement. For years, researchers have been looking to develop an optical transistor, whe... » read more

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