tag: Mentor Graphics

Designing In The Dark
By Jon McDonald - 25 Sep, 2014 - Comments: 0

While power optimization has received significant focus recently, it is still largely a hidden cost to most hardware and software engineers. A significant problem is the lack of visibility into the impact of decisions while decisions are being made. Often an engineer working on a system will have no practical way of measuring the impact of their design decisions on the system power consumption.... » read more

Time To Market Concerns Worsen
By Ed Sperling - 25 Sep, 2014 - Comments: 1

Time to market has always been an issue for chipmakers in highly competitive sectors, but as complexity of chips continues to grow at advanced nodes, and as markets shift increasingly toward consumer electronics, it has jumped to the No. 1 concern. Interviews with engineers at multiple levels inside of some of the largest and midsize chipmakers, conducted by Semiconductor Engineering over th... » read more

Verification Planning And Requirement Tracking For Analog Design
By Mentor, a Siemens Business - 24 Sep, 2014 - Comments: 0

Verifying designs to meet all specifications across all process corners has become an intractable problem from the perspective of debugging, managing, tracking, and meeting verification goals. Implementing a CDV methodology for analog designs can evolve analog design and verification to a standard process-based method that can be tracked and its progress measured. This paper aims to extend comm... » read more

Blog Review: Sept. 24
By Ed Sperling - 24 Sep, 2014 - Comments: 0

Cadence’s Brian Fuller captures Chris Rowen’s phylum classifications for data-efficient design—lots of insects and much bigger but fewer mammals. There are cognitive layers in between, as well. Check out the chart. Mentor’s Robin Bornoff digs into thermal runaway and how to determine when it will occur—and burn up a chip. There’s a video to illustrate just what can go wrong. ... » read more

Who Changes Us
By Anne Cirkel - 19 Sep, 2014 - Comments: 2

Most of us have one of more people that had a huge impact on our life. For me one of those is my former husband, Klaus Cirkel. We met when we were still at university, RWTH Aachen, in western Germany. I was slowly making my way through the metallurgy curriculum. Well, Klaus was the total opposite. He was driven and his drive was infectious. He motivated me to expedite my degree then to take the... » read more

The Week In Review: Design
By Ed Sperling - 19 Sep, 2014 - Comments: 0

Tools Open-Silicon uncorked a 28Gbps SerDes evaluation platform, complete with board, test chip and characterization data, which it says will speed up and simplify development of chips for 100G networks. The chip utilizes PHY IP from Semtech. IP Synopsys rolled out MIPI C-PHY verification IP that utilizes a three-phase coding technique for faster camera, display and SoC interfaces. http://... » read more

Improve Failure Analysis Success Rate With Layout-Aware Diagnosis
By Mentor, a Siemens Business - 18 Sep, 2014 - Comments: 0

In this whitepaper, we explore how a layout-aware diagnosis is a powerful tool for both failure analysis engineers, who find the root cause of a particular failing die, and for yield engineers, who need sets of diagnosis data to find the systematic yield limiters across the life of the product. Logic-based scan test diagnosis is an established software-based methodology for finding the defec... » read more

EDA Vendors Prepare For 7nm
By Ann Mutschler - 18 Sep, 2014 - Comments: 0

It’s not too early to begin looking at design tools for the 7nm, even though the node is not expected to be production-ready until later this decade. While still in the early stages, foundries already in development with leading EDA companies, even though the water remains murky at this point. “7nm right now is in early definition, so we don't know exactly what it will be,” observed... » read more

The Route To Faster Physical Verification And Better Designs
By Jean-Marie Brunet - 18 Sep, 2014 - Comments: 0

By Nancy Nguyen & Jean-Marie Brunet As we’ve moved to today’s leading-edge nodes, physical layout designers have faced more and more challenges to get their design to tape-out on schedule. Timing becomes increasingly difficult to converge, power reduction for both IR and leakage becomes a big issue, and most importantly, how do we meet all of the ever-growing and more complex signoff d... » read more

Blog Review: Sept. 17
By Ed Sperling - 17 Sep, 2014 - Comments: 0

Ansys’ Benoit Debbaut looks at the Pitch drop experiment, which was started in 1927 (yes, that date is correct) to observe the excruciatingly slow movement of a thick liquid weighted down by gravity. Since inception, a total of nine drops have fallen. So when will the tenth drop fall? Place your bets...when you get around to it. Mentor’s Matthew Ballance highlights an interesting challe... » read more

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