tag: Mentor Graphics

Experts At The Table: Verification Strategies
By Ed Sperling - 28 Feb, 2013 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss verification strategies and changes with Harry Foster, chief verification scientist at Mentor Graphics: Janick Bergeron, verification fellow at Synopsys; Pranav Ashar, CTO at Real Intent; Tom Anderson, vice president of marketing at Breker Verification Systems; and Raik Brinkmann, president and CEO of OneSpin Solutions. What follows are ex... » read more

Is This The Era Of Automatic Formal Checks For Verification?
By Graham Bell - 28 Feb, 2013 - Comments: 0

I was thinking about the above question and recalled something IBM would repeat annually back in the late 1980s about its OS/2 replacement for MS-DOS. “This is the year of OS/2!” they would shout. But the marketplace wasn’t listening. As one buddy of mine liked to say, it was only half of an operating system (O.S./2). In the last nine months, my company, Real Intent, along with our com... » read more

Ready For 3D-IC
By Various Writers - 28 Feb, 2013 - Comments: 0

This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon interposers. To download this white paper, click here. » read more

Verifying Complex Chips
By Ed Sperling - 27 Feb, 2013 - Comments: 0

System-Level Design talks about what's changing in SoC verification with Janick Bergeron, verification fellow at Synopsys; Harry Foster, chief verification scientist at Mentor Graphics; Pranav Ashar, chief technology officer at Real Intent; Raik Brinkmann, president and CEO of OneSpin Solutions, and Tom Anderson, vice president of marketing at Breker Verification Systems. [youtube vid=DzDYyf... » read more

The Week In Review: Feb. 25
By Ed Sperling - 25 Feb, 2013 - Comments: 0

By Mark LaPedus Is China set to bail out a U.S. government technology darling? Two Chinese automotive companies, Geely and Dongfeng Motor, are reported to have bid between $200 million and $350 million for a majority stake in Fisker, the maker of plug-in hybrid cars. If that happens Fisker—which has $192 million in U.S. federal government loan guarantees—could be headed to China, according... » read more

Leakage Optimization
By Arvind Narayanan - 24 Feb, 2013 - Comments: 0

By Arvind Narayanan For consumer electronics such as cell phones, tablets, and laptops, long battery life is a key requirement. Battery life is directly related to total power consumption—which is a function of switching activity, capacitance, and voltage—across all operational modes. In full active mode on a cell phone, for example, the dynamic power that comes from signal switching is hi... » read more

Good Pattern Flow Ahead For 14, 10nm
By Ann Mutschler - 21 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node. “They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant... » read more

Accelerating Moore’s Law
By Ed Sperling - 21 Feb, 2013 - Comments: 0

By Ed Sperling Ever since the inception of Moore’s Law, process nodes have moved forward at a rate of once every 18 to 24 months. Companies have been talking about slowing down the rate of progression as things get harder, but at least for the next couple of process nodes something very strange will occur—Moore’s Law will accelerate. The root cause is growing competition for a shrinki... » read more

A New World For Fill At N20
By Mentor Graphics Staff Writers - 21 Feb, 2013 - Comments: 1

By Jeff Wilson and Jean-Marie Brunet There are many drastic changes required to design, verify, and manufacture semiconductors at the 20nm process node (N20). One of these is fill. At previous design nodes, fill was used just to ensure manufacturability by giving each layer (metal, poly, diffusion) an accepted density. At N20, fill is used to address many more manufacturing issues, and has bec... » read more

Optimizing Test To Enable Diagnosis-Driven Yield Analysis
By Various Writers - 21 Feb, 2013 - Comments: 0

Using diagnosis-driven yield analysis, companies have decreased their time to yield, managed manufacturing excursions and recovered yield caused by systematic defects. Dramatic time savings and yield gains have been proven using these methods. Companies must plan ahead to take advantage of diagnosis-driven yield analysis. The planning needs to include how and what patterns to generate during AT... » read more

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