tag: Mentor Graphics

The Fine Art Of Compromise
By Jon McDonald - 19 Dec, 2012 - Comments: 0

By Jon McDonald Ask 10 people a question and you might get 10 different answers. Ask 10 software engineers what they need in a hardware platform and you might get more than 10 different answers because each probably will have a list of needs for the platform to deliver. Getting them to agree on acceptable targets may not be as difficult as a budget compromise, but project failure is a more pe... » read more

Addressing Today’s Complex Clock Modeling Issues With Veloce Emulation Technology
By Various Writers - 19 Dec, 2012 - Comments: 0

Earlier designs were smaller, less complex, and had simpler clocking. A few years back, verification was much easier and clock modeling was not such a big concern. With the drastic increase in the use of System-on-Chip (SoC), designs today are becoming extremely complex with an increasing number of peripherals/external interfaces to consider, requiring a higher numbers of asynchronous clocks. ... » read more

Too Many Rules
By Ed Sperling - 13 Dec, 2012 - Comments: 0

By Ed Sperling The number of restrictive design rules that have to be dealt with by routers at 28nm and beyond has increased by several orders of magnitude compared with several generations ago, creating havoc in the automated tools world and slowing down the entire design process. At a time when market windows are shrinking, complexity is making it harder to meet even the old schedules. Th... » read more

What’s Before Stacked Die?
By Mark LaPedus - 13 Dec, 2012 - Comments: 0

By Mark LaPedus Advanced 2.5D/3D chip stacking has a number of challenges and is still a few years away from mass production. In fact, mass production may not occur until 2015 or 2016. But OEMs can ill afford to sit still and wait for 2.5D/3D technology to mature. So, until 2.5D/3D is ready for prime time, chipmakers and IC-packaging houses are under pressure to innovate and extend current ... » read more

Welcome To The ‘Probably Good Die’ Era
By Mark LaPedus - 13 Dec, 2012 - Comments: 0

By Mark LaPedus In today’s systems, consumers want more performance and bandwidth with a longer battery life. Some chip segments are keeping up with the demands. Still other areas are falling way behind the curve. Battery life is an obvious problem, but memory bandwidth is under the radar. “Initially, memory bandwidth nearly doubled every two years, but this trend has slowed over the pa... » read more

DFM Challenges Abound Below 20nm
By Ed Sperling - 13 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler As semiconductor design teams struggle to wring the last few percentage of die shrink from a technology node, much of the ability to do that rests on the EDA tools. From place and route through DFM checks—essentially, everything that happens before the design is sent to the fab or foundry—it all must be tightly integrated with the manufacturing process so it co... » read more

Double Patterning From Design Enablement To Verification
By Various Writers - 13 Dec, 2012 - Comments: 0

Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal layers. We discuss the unique design and process characteristics of LELE DP, the challenges they present, and various solutions, including: DP design methodologies, current DP conflict feedback mechanisms, and how they can help designers identify and resolve conflicts. E... » read more

Increasing Levels Of Risk
By Ed Sperling - 13 Dec, 2012 - Comments: 0

Semiconductor Manufacturing & Design sits down with Mentor Graphics' Jean-Marie Brunet to talk about double patterning, finFETs, design rules at advanced nodes and why design for manufacturing (DFM) has suddenly become so popular. [youtube vid=3GHvikyjZow] » read more

Eco-Friendly Strategy
By Mentor Graphics Staff Writers - 12 Dec, 2012 - Comments: 0

By Jeff Wilson If you want a winning fill solution at 20nm, you need a robust ecosystem in place with three main players. Each player has a specific role and, particularly as the new technology is defined, the players need to work in close partnership. Why is the ecosystem so important at 20nm? Because of the technological challenges, including process variability and design complexity. The... » read more

Mix-And-Match Power Options
By Ed Sperling - 06 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler Choices abound today when it comes to considering a node shrink. Fully depleted silicon on insulator (FD-SOI) and finFET technologies along with other advanced transistor options are being evaluated, both together and independently of the other. It is possible to implement finFET on bulk 28nm CMOS or finFET on an FD-SOI process, for example. It is also possible to imp... » read more

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