Welcome To The ‘Probably Good Die’ Era

In the era of More than Moore, the existing idea of known good die will likely be replaced; testing remains an issue.

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By Mark LaPedus
In today’s systems, consumers want more performance and bandwidth with a longer battery life.

Some chip segments are keeping up with the demands. Still other areas are falling way behind the curve. Battery life is an obvious problem, but memory bandwidth is under the radar. “Initially, memory bandwidth nearly doubled every two years, but this trend has slowed over the past few years,” said Abe Yee, senior director of advanced technology and package development at Nvidia. “Memory bandwidth has not kept up.”

In fact, there is a growing gap between memory bandwidth and overall system requirements, creating an unwanted I/O bottleneck, Yee said. The memory bandwidth gap, resistance-capacitance (RC) delays and other factors are fueling the development of new 3D DRAM schemes like Wide I/O. “We need Wide I/O memory,” he said. “We also need a known good die stack.”

But advanced chip stacking has a multitude of challenges and is still a few years away from mass production. One of the bigger, and sometimes forgotten, challenges is the ability to obtain and test known good die (KGD). A KGD is an unpackaged part or a bare die that meets a given specification.

As chip complexity increases, the industry may need to lower its targets and not expect a perfect KGD. In other words, the idea of having a KGD may not be attainable. “Ensuring KGD is (expected to be) more difficult in the ‘more than Moore Era,’ “ said Bill Bottoms, chairman and chief executive of ATE vendor Third Millennium Test Solutions (3MTS), in a recent presentation. “The era of known good die is drawing to an end. The concept of known good die will be displaced by ‘probably good die’ for very complex systems.”

Not all is lost, however. To address the KGD problem, the industry is developing a new class of probe cards. Chipmakers also are counting on a range of design-for-test (DFT) technologies, such as boundary scan, built-in-self-test (BIST), redundancy and repair, to enable the “probably good die” era.

Live and let die
KGD became a major issue in the 1980s, when the industry began to push multi-chip modules (MCMs) in systems. In MCMs, several unpackaged dies are stacked or assembled side-by-side within a module as a means to create smaller and faster systems.

MCMs met with limited success and a plethora of startups that were pushing the technology folded in the 1980s and 1990s. “The problem (with MCMs) was the dielectrics,” recalled Richard Otte, president and chief executive of Promex Industries, an IC packaging house. “The dielectrics were crummy.”

The other problem with MCMs was (and still is) the ability to obtain KGD. For years, the industry has procured KGD or bare die for use in MCMs, RF modules and system-in-packages (SIPs). Generally, a bare die takes up less space in a system compared with a traditional packaged part. For this reason, a large percentage of RF chips are sold as bare die and then assembled in RF modules. Analog chips, discretes, memories, MCUs and passives also can be sold as bare die.

Still, IC makers prefer to sell packaged parts, which can be tested in conventional ATE to ensure their quality. Bare die are sometimes viewed as a nuisance because they require specialized testing and handling. As a result, they are sold at a premium.

Selling KGD or bare die “is something chipmakers would prefer not to do,” said Raj Pendse, vice president and chief marketing officer at STATS ChipPAC. “It’s hard to guarantee the quality of KGD. It is sometimes not possible to access all of the test vectors at the die level.”

The challenges escalate for 2.5D/3D designs. In chip stacking, the probability of obtaining KGD decreases. For example, the average yield for a memory wafer is around 50% today, said Robert Patti, chief technology officer for Tezzaron Semiconductor, a 3D DRAM supplier. For a four-layer stacked memory device, the average yield could go as low as 6%, he said, which he described as “not economically viable.”

The inadvertent use of a defective die is catastrophic in 2.5D/3D designs. It will result in yield loss. And in many cases, the entire part must be discarded.

There are other challenges, especially as chipmakers move towards heterogeneous 2.5D/3D designs. In one scenario, an IC maker may use an internal part. Then, the company obtains and integrates a separate bare die from another vendor. But if the device fails in the field, it’s unclear who will take responsibility for the faulty part.

Settling for imperfection
To attack the KGD problem, chipmakers will require breakthroughs on two basic fronts: probe cards and DFT. It also requires a different test flow. The flow for conventional packaged chips includes IC manufacturing, wafer sort, packaging and final test. Wafer sort is considered an initial screening process for packaged ICs.

In contrast, a bare die is not tested at final test using conventional ATE. Instead, a die is tested at wafer sort using a wafer prober. In this flow, chipmakers claim they can achieve a reliable KGD, but overall test costs are sometimes higher. Die failure rates are reduced, but they are never totally eliminated in wafer-level testing.

For 2.5D/3D testing, the industry is working on new probe card technology. A wafer prober is incorporated with a custom probe card, which itself has thousands of probing needles that hit the bond pads on a die. In effect, the prober detects defective die, which are eliminated.

In complex designs, the needles may miss some of the tiny bond pads on the die. The contact force of the needles also could damage the die. Concerning KGD in 2.5D/3D designs, the industry requires “improvements in fine-pitch probe technology,” said Rich Rice, senior vice president of sales for North America at Advanced Semiconductor Engineering (ASE). Specifically, the big challenge for the industry is to develop probe cards that can handle greater than 1,000 contacts and pitches below 50um, Rice said.

In probe cards, there are two basic camps. FormFactor and others are working on fine-pitch probe cards using MEMS-based technology. In another camp, IMEC and Cascade Microtech have been working on a “rocking beam interposer” (RBI) probe card technology. RBI is based on Cascade’s membrane technology. “The metal energy doesn’t bend. It rocks,” said Ken Smith, vice president of technology development at Cascade, a supplier of wafer probers and probe cards.

In RBI, the probe tips are 6um square and 15um tall. With tip forces below 1 gram-force, RBI has demonstrated 40um and below pitches with a pad damage less than 100nm deep. “This technology is still in the early stages of the development cycle,” Smith said during a recent presentation at an event sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC).

Even with breakthroughs in probe cards, 3D test still remains a challenge. In the flow, 3D devices will require at least four more test steps: a pre-bond test before stacking; a mid-bond test in the partial stacking phase; a post-bond test after final stacking; and a final test. The interposer and TSVs may also require separate testing.

Conventional ATE cannot be used in many, or possibly any, of these steps. So test must start in the design phase with various DFT techniques. In one scenario envisioned by Mentor Graphics, boundary scan can be used to test the bottom die in a 2.5D/3D design. Embedded core test can be used to test the middle or other dies, according to Mentor.

“The bigger challenge is with stacked logic die,” said Steve Pateras, product marketing director at Mentor. “There are a number of issues there. One is the known-good die problem. How do you ensure you’re getting good die when you stack them together? With bare logic die, particularly with heterogeneous parts, the quality of those parts comes into question.”

For years, memory makers have made use of BIST, repair and redundancy in their 2D designs, which may translate in the 2.5D/3D world. “With memory it’s easier, because there’s a robust testing methodology for bare memory die. The JEDEC memories have scan chains in them, which is one way of testing the memories and the SoC. You can use memory BIST,” Pateras said.

Using such techniques, 3D DRAM maker Tezzaron claims to have obtained better yields in 3D over 2D. “You have to change the way you think about design,” said Tezzaron’s Patti. “The secret to KGD is design-for-repair.”

Tezzaron refers to its design-for-repair and BIST solution as “BiSTAR.” Designed to repair bad memory cells and ensure a known good memory stack, BiSTAR includes 256 BIST sequencers, which run independently in parallel.

Besides repair and BIST, Patti said the industry must rethink its definition of KGD and may need to settle for something less. “Will we ever have 100% perfect KGD? It’s probably not practical,” he said. “A ‘kind of a good die’ may be acceptable. We may also have to accept the idea of having ‘not bad die.’”