tag: Mentor Graphics

The Essential Tool Kit
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler Is there an essential chip design tool kit today that has only the ‘must haves?’ Sure, this sounds like a straightforward question, but the answer really depends on what process node the design will be manufacturing on. According to Jon McDonald, technical marketing engineer for the design and creation business at Mentor Graphics, there’s actually nothi... » read more

The Growing Confidence Gap In Verification
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ed Sperling It’s no surprise that verification is getting more difficult at each new process node. What’s less obvious is just how deep into organizations the job of verifying SoCs and ASICs now extends. Functional verification used to be a well-defined job at the back end of the design flow. It has evolved into a multi-dimensional, multi-group challenge, beginning at the earliest st... » read more

The Real Value Of Test
By Jon McDonald - 25 Oct, 2012 - Comments: 0

By Jon McDonald Sometimes one test is worth a thousand code reviews. Perhaps not a thousand, but it is a very significant number. Not that this is a new idea, but I’ve had a couple of experiences recently that reminded me how valuable a transaction-level simulation model is as an executable specification. In one case we were reviewing aspects of a potential design change, trying to decide... » read more

Challenges For Patterning Process Models Applied To Large Scale
By Various Writers - 25 Oct, 2012 - Comments: 0

Full-chip patterning simulation has been a key enabler for multiple technology generations, from 130 nm to the emerging 14 nm node. This span has featured two wavelength changes, a progression of optical NA increases (and a subsequent decrease), and a variety of patterning processes and chemistries. Full-chip patterning simulations utilize quasi-rigorous optical models and semi-empirical resist... » read more

Challenges Of Physical Design Closure
By Jean-Marie Brunet - 22 Oct, 2012 - Comments: 0

By Jean-Marie Brunet A clear trend in IC design is that with each smaller process node, reaching design closure gets more difficult, expensive, and time consuming. Printing ever-smaller features with 193nm wavelength light has introduced unprecedented levels of manufacturing challenges, which are addressed with a growing set of complex design rules (DRC) and design for manufacturing (DFM) cons... » read more

Experts At The Table: Issues In Lithography
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Juan Rey, senior director of engineering at Mentor Graphics; Aki Fujimura, chairman and chief executive at D2S; and Tatsuo Enami, general manager for the sales division at Gigaphoton. What follows are excerpts of that conversation. SMD: What are the big challenges in lithography?... » read more

Design For Power
By Ed Sperling - 11 Oct, 2012 - Comments: 0

By Ed Sperling Figuring out a single power budget and mapping out what has become known as holistic power intent for an SoC sounds great on paper, but reality has turned out to be somewhat different. While system architects still call the shots on how a chip is designed, there is a lot more information flowing in all directions further down the design chain these days. Unlike functionality,... » read more

The Trouble With Clock Trees
By Arvind Narayanan - 11 Oct, 2012 - Comments: 0

By Arvind Narayanan Among the perennial challenges of advanced-node IC design is power reduction. Clock trees are now the single largest source of dynamic power consumption, which makes clock tree synthesis (CTS) and optimization an important task for achieving overall power savings. Building a well-balanced clock tree and effectively managing clock skew has been a challenge since the first... » read more

Choosing The Right Kite
By Jon McDonald - 27 Sep, 2012 - Comments: 0

By Jon McDonald At my 16-year-old son’s suggestion the two of us have been taking kite-surfing lessons. Last weekend part of the lesson covered the different kinds of kites, how they compare and reasons to use one versus another. One of the points made by the instructor was the need to have different kites for different conditions. It’s such a simple concept, but one that was forgotten ... » read more

Where Does It Hurt?
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ed Sperling The IC design industry is feeling a new kind of pain—this one driven by uncertainty over architectural shifts, new ecosystem interactions and new ways to account for costs. As mainstream ICs move from 50/45/40nm to around 32/28/22nm, there are only two choices for design teams—continue shrinking features or stack dies. In many cases, the ultimate solution may be a combina... » read more

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