tag: Mentor Graphics

Different Ways To Boost Yield
By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler In the race to get products to market with shortening product cycles, steepening the ramp to yield is critical. The introductory phase of a product is the point at which margins are highest and market share can be most easily gained. This is no surprise to chipmakers. What is surprising is just how much more difficult it has become to achieve acceptable yield quick... » read more

Virtual Prototyping Takes Off
By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler Skyrocketing software development costs, which for years have been “somebody else’s problem,” are now firmly part of the SoC development teams list of headaches. That has made virtual prototyping far more popular, particularly at 40nm and beyond, where engineers are looking at this approach as a way of managing complexity, doing architectural exploration and eve... » read more

Management Buys Into ESL
By Jon McDonald - 30 Jun, 2011 - Comments: 0

By Jon McDonald Over the past few weeks I've spent a significant amount of time at industry shows, the largest of which is DAC. It was interesting to hear the tone of the conversations this year around ESL. ESL has reached a level of acceptance such that it is now being co-opted and interpreted to cover an amazing array of activities. I have felt for a while that the electronic design indus... » read more

The Tao Of Software
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ed Sperling and Pallab Chatterjee As software teams continue to race past hardware teams in numbers of engineers, hours spent on designs and NRE budgets, companies are beginning to question whether there needs to be a fundamental shift in priorities and strategy. The problem is that it takes far too long to write and debug the software and to get it working on the hardware, even with vir... » read more

Managing Physical Effects
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler Managing the physical effects from manufacturing is becoming increasingly critical as designs grow in size and process geometries dive lower. Just keeping track of these effects in a billion-gate design is a daunting task. At advanced manufacturing nodes, the capacitance and inductance effects make the design much harder—and that includes both on-die and off-die ... » read more

The Tough Metric: Energy-Efficiency
By Barry Pangrle - 16 Jun, 2011 - Comments: 0

By Barry Pangrle Jem Davies, fellow and vice president of technology at ARM, gave a keynote address on Computing Power and Energy-Efficiency Tuesday morning at the AMD Fusion Developer Summit in Bellevue, Washington. His scheduled appearance at the summit led to much speculation and rumor a while back, especially within the context of the ARM versus x86 battle for market share in the tablet ar... » read more

Low-Power Solutions At DAC
By Bhanu Kapoor - 16 Jun, 2011 - Comments: 0

By Bhanu Kapoor Power is the main driver of semiconductor process technology related advances recently. One would expect a similar focus in the electronic design automation industry to help designers implement low power designs. However, the latest DAC in San Diego didn’t give the impression that the EDA industry is thinking likewise, perhaps with the exception of verification aspects of low... » read more

Physical Effects Affecting Design
By Ann Mutschler - 16 Jun, 2011 - Comments: 0

With the increase in analog content in today’s designs, the industry is facing a real challenge in terms of how to perform mixed-signal verification at the functional level, at the SPICE level and down to physical implementation of the DRC rules. Joseph Davis, product manager for Calibre interactive and integration products at Mentor Graphics, explained there are three things driving what�... » read more

Experts At The Table: Power Budgeting
By Ed Sperling - 03 Jun, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions; Matt Klein, principal engineer for power and broadcast applications at Xilinx; and Paul ... » read more

Double Patterning: Sharing the Benefit and the Burden
By David Abercrombie - 01 Jun, 2011 - Comments: 0

By David Abercrombie Share and share alike! Our mothers always said it was the right thing to do, and it seems that this ideology is now coming front and center for double patterning at 20nm and below. As we continue to shrink the metal pitch from node to node, we also push the lithography k1 lower and lower, since we are currently stuck with 193nm/1.35NA scanners. When k1 dropped below 0.6,... » read more

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