tag: Mentor

STMicroelectronics Methodology And Process For Heterogeneous Automotive Package Design
By Siemens EDA - 06 Oct, 2021 - Comments: 0

As a leading supplier of automotive semiconductors, STMicroelectronics must continue to move fast to develop and deliver leading-edge solutions. Employing package design as part of system innovation requires the STMicroelectronics Back-End Manufacturing Technology R&D organization to embrace the key driving forces of product development. In the automotive field, package designers need to... » read more

Blog Review: Oct. 6
By Jesse Allen - 06 Oct, 2021 - Comments: 0

Arizona State University's Jae-sun Seo and Arm's Paul Whatmough introduce a fully-parallel and fully-pipelined FPGA accelerator for sparse CNNs that can eliminate off-chip memory access and also efficiently support elementwise pruning of CNN weights. Cadence's Paul McLellan highlights trends seen at the recent Hot Chips, from machine learning and advanced packaging driving higher performance... » read more

Week In Review: Design, Low Power
By Jesse Allen - 01 Oct, 2021 - Comments: 0

Valens Semiconductor began trading on the New York Stock Exchange as VLN after a merger with special-purpose acquisition company (SPAC) PTK Acquisition Corp. Valens offers high-speed connectivity chips for the audio-video and automotive markets, including its HDBaseT technology for connectivity between ultra-HD video sources and remote displays and its in-vehicle high-speed links. The transacti... » read more

Optimizing AI Systems
By Ed Sperling - 29 Sep, 2021 - Comments: 0

Inserting AI and machine learning into chips adds a whole new dimension of complexity, and creates a variety of potential problems, including deadlocks, loss of performance, and difficulty in achieving closure on many fronts. Gajinder Panesar, fellow at Siemens EDA, talks with Semiconductor Engineering about what’s changed and how to optimize these new devices and systems by monitoring them f... » read more

Blog Review: Sept. 29
By Jesse Allen - 29 Sep, 2021 - Comments: 0

Cadence's Paul McLellan checks out two of the biggest chips presented at the recent Hot Chips: a graphics chip from Intel for an upcoming supercomputer and Cerebras' wafer-scale AI chip. Synopsys' Datsen Davies Tharakan lists the top five design challenges for electric vehicles and power semiconductors and why a robust design flow can accelerate the growth of hybrid and electric vehicles goi... » read more

EDA Vendors Widen Use Of AI
By Ed Sperling - 29 Sep, 2021 - Comments: 0

EDA vendors are widening the use of AI and machine learning to incorporate multiple tools, providing continuity and access to consistent data at multiple points in the semiconductor design flow. While gaps remain, early results from a number of EDA tools providers point to significant improvements in performance, power, and time to market. AI/ML has been deployed for some time in EDA. Still,... » read more

Software-Hardware Co-Design Becomes Real
By Brian Bailey - 27 Sep, 2021 - Comments: 1

For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some of the basics. Hardware/software co-design is essentially a bottom-up process, where hardware is deve... » read more

Can We Efficiently Automate 2.5/3D IC ESD Protection Verification?
By Dina Medhat - 23 Sep, 2021 - Comments: 0

Protection against ESD events (commonly referred to as ESD robustness) is an extremely important aspect of integrated circuit (IC) design and verification, including 2.5/3D designs. ESD events cause severe damage to ICs due to a sudden and unexpected flow of electrical current between two electrically charged objects. This current may be caused by contact, an electrical short, or dielectric bre... » read more

Automated ESD Protection Verification For 2.5D And 3D ICs
By Siemens EDA - 22 Sep, 2021 - Comments: 0

While automated flows for ESD protection verification are well-established for 2D ICs, 2.5D and 3D designs present new challenges in both ESD circuit design and verification. Advanced automated ESD verification methodology accurately and effectively evaluates ESD protection in 2.5/3D IC designs. Ensuring correct and consistent ESD protection in 2.5/3D ICs raises the reliability and product life... » read more

Blog Review: Sept. 22
By Jesse Allen - 22 Sep, 2021 - Comments: 0

Ansys' Tyler Ferris describes some of the many ways electronics on a PCB assembly can fail, from component level failures like wirebond breaking and liftoff to board-level failures such as conductive anodic filament failure. Cadence's Paul McLellan considers the switch from low-speed parallel interfaces to high-speed serial interfaces as one of the key advancements making modern data centers... » read more

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