EDA Tools For Quantum Chips

By Marie C. Baca - 22 Nov, 2022 - Comments: 0

Commercially viable quantum computers are at least several years away, but some researchers already are questioning whether existing EDA tools will be sufficient for designing quantum chips and systems. That’s because quantum design requirements at times transcend classical rules about materials, temperature, and structure — rules that are foundational for the majority of EDA products on th... » read more

The Drive Toward Virtual Prototypes

By Brian Bailey - 22 Nov, 2022 - Comments: 1

Chipmakers are piling an increasing set of demands on virtual prototypes that go well beyond its original scope, forcing EDA companies to significantly rethink models, abstractions, interfaces, view orthogonality, and flows. The virtual prototype has been around for at least 20 years, but its role has been limited. It has largely been used as an integration and analysis platform for models t... » read more

Blog Review: Nov. 16

By Jesse Allen - 16 Nov, 2022 - Comments: 0

Siemens EDA's Jake Wiltgen explains the difference between transient and permanent faults when designing to the ISO 26262 standard, including where they come from and key ways to protect against them. Synopsys' Vikas Gautam points to how the economics of designing large SoCs is driving chiplet-based designs and the need for die-to-die standards such as UCIe, along with the key protocol verif... » read more

Improving Reliability In Automobiles

By John Koon - 14 Nov, 2022 - Comments: 0

Carmakers are turning to predictive and preventive maintenance to improve the safety and reliability of increasingly electrified vehicles, setting the stage for more internal and external sensors, and more intelligence to interpret and react to the data generated by those sensors. The number of chips inside of vehicles has been steadily rising, regardless of whether they are powered by elect... » read more

Week In Review: Semiconductor Manufacturing, Test

By Karen Heyman - 11 Nov, 2022 - Comments: 0

U.S. President Joe Biden appears ready to increase pressure on Japan and the Netherlands to help block the flow of advanced chip technology to China, where it can be used to develop cutting-edge weapons. "You will see Japan and Netherlands follow our lead," U.S. Commerce Secretary Gina Raimondo told CNBC. Japan plans to budget ¥350 billion ($2.38 billion) in a research collaboration with th... » read more

Taking Power Much More Seriously

By Brian Bailey - 10 Nov, 2022 - Comments: 0

An increasing number of electronic systems are becoming limited by thermal issues, and the only way to solve them is by elevating energy consumption to a primary design concern rather than a last-minute optimization technique. The optimization of any system involves a complex balance of static and dynamic techniques. The goal is to achieve maximum functionality and performance in the smalles... » read more

Are You Paying Proper Attention To Your ESD Design Windows?

By Derong Yan - 10 Nov, 2022 - Comments: 0

Electrostatic discharge (ESD) issues in integrated circuit (IC) chip designs have become more critical at advanced semiconductor process nodes, due to shrinking transistor dimensions and oxide layer thickness [1]. There are many ESD design rules and flows that designers check for common ESD issues, such as topological checks for the existence of ESD protection devices, current density (CD) chec... » read more

Solving Thermal Coupling Issues In Complex Chips

By Ann Mutschler - 10 Nov, 2022 - Comments: 0

Rising chip and packaging complexity is causing a proportionate increase in thermal couplings, which can reduce performance, shorten the lifespan of chips, and impact overall reliability of chips and systems. Thermal coupling is essentially a junction between two devices, such as a chip and a package, or a transistor and a substrate, in which heat is transferred from one to the other. If not... » read more

Balancing Power And Heat In Advanced Chip Designs

By Karen Heyman - 10 Nov, 2022 - Comments: 1

Power and heat use to be someone else's problem. That's no longer the case, and the issues are spreading as more designs migrate to more advanced process nodes and different types of advanced packaging. There are a number of reasons for this shift. To begin with, there are shrinking wire diameters, thinner dielectrics, and thinner substrates. The scaling of wires requires more energy to driv... » read more

Weird Incidents Reveal L5 Challenges

By Marie C. Baca - 09 Nov, 2022 - Comments: 0

A series of surprising, counterintuitive, and sometimes bizarre incidents reveal the challenges of achieving full Level 5 autonomy in self-driving vehicles, which are an increasingly common site in major cities. While it’s easy to dismiss such anecdotes as humorous glitches compared with the sobering accounts of autonomous tech-related injuries and fatalities, industry executives say these oc... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?