tag: nanosheets

Synchrotron S-ray Diffraction-based Non-destructive Nanoscale Mapping of Si/SiGe Nanosheets for GAA structures
By Technical Paper Link - 13 Jun, 2022 - Comments: 0

New research paper titled "Mapping of the mechanical response in Si/SiGe nanosheet device geometries" from researchers at IBM T.J. Watson Research Center and Brookhaven National Laboratory. Sponsored by U.S. DOE. Abstract "The performance of next-generation, nanoelectronic devices relies on a precise understanding of strain within the constituent materials. However, the increased flexibilit... » read more

Scalable Approach to Fabricate Memristor Arrays at Wafer-scale
By Technical Paper Link - 06 Jun, 2022 - Comments: 0

New technical paper titled "Wafer-scale solution-processed 2D material analog resistive memory array for memory-based computing" from researchers at National University of Singapore and Institute of High Performance Computing, Singapore. Abstract "Realization of high-density and reliable resistive random access memories based on two-dimensional semiconductors is crucial toward their develop... » read more

Inside Intel’s Ambitious Roadmap
By Mark LaPedus and Ed Sperling - 23 Aug, 2021 - Comments: 2

Ann Kelleher, senior vice president and general manager of Technology Development at Intel, sat down with Semiconductor Engineering to talk about the company’s new logic roadmap, as well as lithography, packaging, and process technology. What follows are excerpts of that discussion. SE: Intel recently disclosed its new logic roadmap. Beyond Intel 3, the company is working on Intel 20A. Wit... » read more

Impact Of GAA Transistors At 3/2nm
By Brian Bailey - 16 Aug, 2021 - Comments: 2

The chip industry is poised for another change in transistor structure as gate-all-around (GAA) FETs replace finFETs at 3nm and below, creating a new set of challenges for design teams that will need to be fully understood and addressed. GAA FETs are considered an evolutionary step from finFETs, but the impact on design flows and tools is still expected to be significant. GAA FETs will offer... » read more

Thinner Channels With 2D Semiconductors
By Katherine Derbyshire - 21 Jun, 2021 - Comments: 0

Moving to future nodes will require more than just smaller features. At 3/2nm and beyond, new materials are likely to be added, but which ones and exactly when will depend upon an explosion of material science research underway at universities and companies around the globe. With field-effect transistors, a voltage applied to the gate creates an electric field in the channel, bending the ban... » read more

Challenges At 3/2nm
By Ed Sperling - 15 Sep, 2020 - Comments: 0

David Fried, vice president of computational products at Lam Research, talks about issues at upcoming process nodes, the move to EUV lithography and nanosheet transistors, and how process variation can affect yield and device performance. » read more

Introducing Nanosheets Into Complementary-Field Effect Transistors (CFETs)
By Benjamin Vincent - 01 Jun, 2020 - Comments: 0

In our November 2019 blog [1], we discussed using virtual fabrication (SEMulator3D) to benchmark different process integration options for Complementary-FET (CFET) fabrication. CFET is a CMOS architecture that was proposed by imec in 2018 [2]. This architecture contains p- and n-MOSFET structures built on top of each other, instead of having them located side-by-side. In our previous blog, we r... » read more

Moving To GAA FETs
By Katherine Derbyshire - 20 Feb, 2020 - Comments: 2

How do you measure the size of a transistor? Is it the gate length, or the distance between the source and drain contacts? For planar transistors, the two values are approximately the same. The gate, plus a dielectric spacer, fits between the source and drain contacts. The contact pitch, limited by the smallest features that the lithography process can print, determines how many transistors ... » read more

EDA In The Cloud
By Ed Sperling - 18 Feb, 2020 - Comments: 0

Michael White, director of product marketing for Calibre physical verification at Mentor, a Siemens Business, looks at the growing compute requirements at 7, 5 and 3nm, why the cloud looks increasingly attractive from a security and capacity standpoint, and how the cloud as well as new lithography will affect the cost and complexity of developing new chips. » read more

Variation Issues Grow Wider And Deeper
By Ed Sperling - 24 Jan, 2019 - Comments: 0

Variation is becoming more problematic as chips become increasingly heterogeneous and as they are used in new applications and different locations, sparking concerns about how to solve these issues and what the full impact will be. In the past, variation in semiconductors was considered a foundry issue, typically at the most advanced process node, and largely ignored by most companies. New p... » read more

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